Timing Analysis

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Application Notes
Application Briefs
XCELL Articles

to view the PDF files below.

Application Notes

Title	Size
Set-up and Hold Times	12 kB
Using the XC9500 Timing Model	65 kB
Metastable Recovery (FPGAs)	29 kB
Metastability Considerations (CPLDs)	35 kB
Overshoot and Undershoot	8 kB
LCA Speed Estimation: Asking the Right Question	8 kB
Estimating the Performance of XC4000E Adders and Counters	37 kB
Improving XC4000 Design Performance	165 kB
XC4000 Series Technical Information (Capacitive Loading, Ground Bounce)	35 kB
XC3000 Series Technical Information (I/O Characteristics, Oscillator)	108 kB

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Application Briefs

Title	Size
PLL Design Techniques and Usage in FPGA Design	37 kB

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XCELL Articles

Title	Issue
Trouble-Free Switching Between Clocks	Q1 '97
A Look at "Minimum" Delays	Q2 '96
Power, Package, and Performance: Trading Off Among the Three P's	Q3 '96
Metastability Recovery in Xilinx FPGAs	Q3 '96
Using Decoupling Capacitors	Q1 '96
Minimizing Power Consumption in FPGA Designs	Q4 '95
Synchronous RAM Timing in the XC4000E FPGA	Q4 '95
User-Defined Schmitt Triggers	Q4 '95
Overshoot and Undershoot	Q3 '95
Low-Pass Filtering of Noisy Inputs	Q3 '95
Hold is a Four-Letter Word	Q3 '95