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| Title | Size | Summary | Family | Design |
|---|---|---|---|---|
| Using
In-System Programmability in Boundary-Scan Systems |
66 kB | XAPP070 | XC9500 | |
| Using
the XC9500 Timing Model |
63 kB | XAPP071 | XC9500 | |
| XC9500
Design Optimization |
71 kB | XAPP072 | XC9500 | |
| Designing
with XC9500 CPLDs |
104 kB | XAPP073 | XC9500 | |
| Pin
Preassigning with XC9500 CPLDs |
80 kB | XAPP074 | XC9500 | |
| Using
ABEL with Xilinx CPLDs |
125 kB | XAPP075 | XC9500 | |
| Embedded
Instrumentation Using XC9500 CPLDs |
52 kB | XAPP076 | XC9500 | |
| Metastability
Considerations |
33 kB | XAPP077 | XC9500 | |
XC9536
ISP Demo Board  |
54 kB | XAPP078 | XC9500 | ABEL
VHDL |
| CPLD-Based
1Mbit Virtual SPROM Downloader for XC4000-Series FPGAs |
69 kB | XAPP079 | XC7300 XC9500 |
ABEL |
XAPP004
Loadable Binary Counters
The design strategies for loadable and non-loadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter. Up, down and up/down counters are described, with lengths of 16 and 32 bits. Design files are available for all six versions.
XAPP005
Register-Based FIFO
While XC3000-series LCA devices do not provide RAM, it is possible to construct small register-based FIFOs. A basic synchronous FIFO requires one CLB for each two bits of FIFO capacity, plus one CLB for each word in the FIFO. Optional asynchronous input and output circuits are provided. Design files are available for two implementations of this design. The fastest of the two implementations uses a constraints file to achieve better placement.
XAPP007
Boundary-Scan Emulator for XC3000
CLBs are used to emulate IEEE 1149.1 Boundary Scan. The LCA device is configured to test the board interconnect, and then reconfigured for operation.
XAPP009
Harmonic Frequency Synthesizer and FSK Modulator
Harmonic Frequency Synthesizer:
Uses an accumulator technique to generate frequencies that are evenly spaced
harmonics of some minimum frequency. Extensive pipelining is employed to
permit high clock rates.
FSK Modulator:
A modification of the Harmonic Frequency Synthesizer that automatically
switches between two frequencies in accordance with an NRZ input.
XAPP010
Bus-Structured Serial Input/Output Device
Simple shift registers are used to illustrate how 3-state busses may be used within an LCA device. Dedicated wide decoders are used to decode an I/O address range and enable the internal registers.
XAPP011
LCA Speed Estimation: Asking the Right
Question
A simple algorithm is described for determining the depth of logic, in CLBs, that can be supported at a given clock frequency. The algorithm is suitable for XC3000/XC3100 or XC4000 LCA devices.
XAPP012
Quadrature Phase Detector
A simple state machine is used to adapt the output of two photo-cells to control an up/down counter. The state machine provides hysteresis for counting parts correctly, regardless of changes in direction.
XAPP013
Using the Dedicated Carry Logic in XC4000E
This Application Note describes the operation of the XC4000E dedicated carry logic, the standard configurations provided for its use, and how these are combined into arithmetic functions and counters.
XAPP014
Ultra-Fast Synchronous Counters
This fully synchronous, non-loadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small Longline delay is eliminated, resulting in the fastest possible synchronous counter.
XAPP015
Using the XC4000 Readback Capability
Xilinx Family This Application Note describes the XC4000 Readback capability and its use. Topics include: initialization of the Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back LCA devices, and Cyclic Redundancy Check (CRC).
XAPP017
Boundary Scan in XC4000 and XC5000 Series
Devices
XC4000/XC5000 FPGA devices contain boundary-scan facilities that are compatible with IEEE Standard 1149.1. This Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an FPGA design.
XAPP018
Estimating the Performance of XC4000E Adders
and Counters
Using the XC4000E dedicated carry logic, the performance of adders and counters can easily be predicted. This Application Note provides formulae for estimating the performance of such adders and counters.
XAPP022
Adders, Subtracters and Accumulators in XC3000
This Application Note surveys the different adder techniques that are available for XC3000 designs. Examples are shown, and a speed/size comparison is made.
XAPP023
Accelerating Loadable Counters in XC4000
The XC4000 dedicated carry logic provides for very compact, high-performance counters. This Application Note describes a technique for increasing the performance of these counters using minimum additional logic. Using this technique, the counters remain loadable.
XAPP026
Multiplexers and Barrel Shifters in XC3000/XC3100
This Application Note provides guidance for implementing high performance multiplexers and barrel shifters in XC3000 LCA devices.
XAPP027
Implementing State Machines in LCA Devices
This Application Note discusses various approaches that are available for implementing state machines in LCA devices. In particular, the one-hot-encoding scheme for medium-sized state machines is discussed.
XAPP028
Frequency/Phase Comparator for Phase-Locked
Loops
The phase comparator described in this Application Note permits phase-locked loops to be constructed using LCA devices that only require an external voltage-controlled oscillator and integrating amplifier.
XAPP029
Serial Code Conversion Between BCD and
Binary
Binary-to-BCD and BCD-to-binary conversions are performed between serial binary values and parallel BCD values.
XAPP030
Megabit FIFO in Two Chips: One LCA Device
and One DRAM
This Application Note describes the use of an LCA device as an address controller that permits a standard DRAM to be used as deep FIFO.
XAPP043
Improving XC4000 Design Performance
This Application Note describes XC4000 architectural features that can be exploited in high-performance designs, and software techniques that improve placement, routing and timing. It also contains information necessary for advanced design techniques, such as floor planning, locking down I/Os, and critical path optimization.
XAPP044
High-Performance RAM-Based FIFO
Two FIFO designs are described. In both cases, arbitration permits any RAM cycle to be a PUSH or a POP. XC4000 RAM performance is improved through read-modify-write operation, and the fastest clock required is at the RAM-cycle rate. The first design is expandable to any size FIFO, while the second, faster design is restricted to 16 or 32 words.
XAPP051
Synchronous and Asynchronous FIFO Designs
This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000-Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. Emphasis is on the fast, efficient and reliable generation of the handshake signals FULL and EMPTY, which determine design performance.
XAPP052
Efficient Shift Registers, LFSR Counters,
and Long Pseudo-Random Sequence Generators
Shift registers longer than eight bits can be implemented most efficiently in XC4000E Select-RAMTM . Using Linear Feedback Shift-Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and pseudo-random sequence generators with repetition rates of thousands and even trillions of years, useful for testing and encryption purposes. The appropriate taps for maximum-length LFSR counters of up to 168 bits are listed.
XAPP053
Implementing FIFOs in XC4000 Series RAM
This Application Note demonstrates how to use the various RAM modes in XC4000-Series logic blocks. A simple FIFO is implemented in several different ways, using combinations of level-sensitive (asynchronous) and edge-triggered (synchronous), single-port and dual-port RAM.
XAPP054
Constant Coefficient Multipliers for the
XC4000E
This paper identifies two points at which constant coefficient multipliers become the optimum choice in DSP, and implements constant (k) coefficient multipliers (KCMs) in the XC4000E. It also reveals the solution to an interesting design problem which emerges. There are additional enhancements since the original paper, introducing a hybrid technique, was first published in 1993.
XAPP055
Block Adaptive Filter
This application note describes a specific design for implementing a high-speed, full-precision, adaptive filter in the XC4000E/EX family of FPGAs. The design may be easily modified, and demonstrates the suitability of using FPGAs in digital signal processing applications. This application note is based on a 12-bit data, 12-bit coefficient, full-precision, block adaptive filter design. This design can be modified to accommodate different data and coefficient sizes, as well as lesser precision. The application note covers how to modify the design including the trade-offs involved. The filter is engineered for use in the XC4000 Series.
XAPP056
System Design with New XC4000EX I/O Features
The XC4000EX FPGA family provides several new I/O features, including an additional latch on each input and an output multiplexer on each output. The output multiplexer can also be configured as a two-input function generator. Three different types of clock buffers allow system timing flexibility. These features are discussed, and examples show how to use them.
XAPP057
Using Select-RAM Memory in XC4000 Series
FPGAs
XC4000-Series FPGAs include Select-RAMTM memory, which can be configured as ROM or as single- or dual-port RAM, with edge-triggered or level-sensitive timing. This application note describes how to implement Select-RAM memory in a design: in schematic entry, MemGen memory block generator, X-BLOXTM schematic-based synthesis, and HDL-synthesis environments. Specifying timing requirements, evaluating performance, and floorplanning are also described.
XAPP058
XC9500 In-System Programming Using an 8051
Microcontroller
The XC9500 high performance CPLD family provides in-system programmability, reliable pin locking, and JTAG boundary-scan test capability. This powerful combination of features allows designers to make significant changes and yet keep the original device pinouts, eliminating the need to re-tool PC boards. By using an embedded controller to program these CPLDs from an on-board RAM or EPROM, designers can easily upgrade, modify, and test designs, even in the field.
XAPP059
Gate Count Capacity Metrics for FPGAs
Three metrics are defined to describe FPGA device capacity: Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine these values is described.
XAPP060
Design Migration from XC4000 to XC5200
The XC5200 delivers the most cost-effective solution for high-density, reprogrammable logic designs not requiring the dedicated XC4000 Select-RAMTM, system features, or very high performance levels. This Application Note reviews the differences between the XC5200 and XC4000 families, recommends approaches for converting XC4000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.
XAPP061
Design Migration from XC2000/XC3000 to XC5200
The XC5200 delivers the most cost-effective solution for high-density, reprogrammable logic designs not requiring the dedicated XC4000 Select-RAMTM, or very high performance of the XC3100A and XC4000 Series. This Application Note reviews the differences between the XC5200 and XC2000/XC3000 families, recommends approaches for converting XC2000/XC3000 designs to the XC5200 architecture, and provides a methodology to migrate designs easily in multiple CAE environments.
XAPP062
Design Migration from XC4000 to XC4000E
The XC4000E is an enhanced architecture based on the XC4000 family, but offers many new features, particularly Select-RAMTM memory. When converting XC4000, XC4000A, XC4000D, and XC4000H designs, the XC4000E is an excellent choice. The conversion process may be as simple as downloading the same bitstream into the XC4000E device (XC4000 and XC4000D bitstreams only), or it may involve changes to the schematic or HDL code. This Application Note describes techniques that should be employed to convert from any of the XC4000, XC4000A, XC4000D, or XC4000H families to the XC4000E family.
XAPP063
Interfacing XC6200 To Microprocessors (MC68020
Example)
The issues involved in interfacing XC6200 family members to microprocessors are discussed. An example using the Motorola 68020 processor is described.
XAPP064
Interfacing XC6200 To Microprocessors (TMS320C50
Example)
The issues involved in interfacing XC6200 family members to microprocessors are discussed. An example using the TMS320C50 processor is described.
XAPP065
XC4000 Series Edge-Triggered and Dual-Port
RAM Capability
The XC4000E and XC4000EX FPGA families provide distributed on-chip RAM. Select-RAMTM memory can be configured as level-sensitive or edge-triggered, single-port or dual-port RAM. The edge-triggered capability simplifies system timing and provides better performance for RAM-based designs. The dual-port mode offers new capabilities and simplifies FIFO designs.
XAPP066
Design Migration with XC9500 CPLDs
The Xilinx FastFLASH technology, used in the XC9500 family, provides key advantages in reliability, density, and performance. This overview describes the FastFLASH process technology and compares it with EEPROM technology.
XAPP067
Using Automatic Test Equipment to Program
XC9500 Devices In-System
This application note describes how to program XC9500 devices in-system, using standard automatic test equipment.
XAPP068
In-System Programming Times
This application note discusses the in-system programming speed of the XC9500 devices.
XAPP069
Using the XC9500 JTAG Boundary-Scan
Interface
This application note explains the XC9500 boundary-scan interface and demonstrates the software available for programming and testing XC9500 CPLDs. An appendix summarizes JTAG operations and overviews the additional operations supported by XC9500 CPLDs for in-system programming.
XAPP070
Using In-System Programmability in Boundary-Scan
Systems
This application note discusses basic design considerations for in-system programming of multiple XC9500 devices in a boundary-scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices.
XAPP071
Using the XC9500 Timing Model
This application note describes how to use the XC9500 timing model. All XC9500 CPLDs have a uniform architecture and an identical timing model, making them very easy to use and understand. To determine specific timing details, users need only compare their paths of interest to the architectural diagrams and, using the timing model presented here, perform a simple addition of incremental time delays.
XAPP072
XC9500 Design Optimization
This application note shows the tradeoffs that can be made to gain the greatest possible densities and speeds for schematic, behavioral, and VHDL implementations.
XAPP073
Designing with XC9500 CPLDs
This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices.
XAPP074
Pin Preassigning with XC9500 CPLDs
This application note describes the planning required for successful pin preassigning and gives a detailed example.
XAPP075
Using ABEL with Xilinx CPLDs
This application note provides a basic overview of the ABEL language and gives examples showing how to use ABEL to fully utilize the specific features of Xilinx CPLDs.
XAPP076
Embedded Instrumentation Using XC9500 CPLDs
This application note shows how to build embedded test instruments into XC9500 CPLDs.
XAPP077
Metastability Considerations
Metastability is unavoidable in asynchronous systems. However, using the formulas and test measurements supplied here, designers can calculate the probability of failure. Design techniques for minimizing metastability are also provided.
XAPP078
XC9536 ISP Demo Board
The demo board described in this application note is a tool for demonstrating the In-System Programming (ISP) capabilities of the XC9500 CPLD family.
XAPP079
CPLD-Based 1Mbit Virtual SPROM Downloader
for XC4000-Series FPGAs
This application note describes the design of a very low cost, CPLD-based virtual SPROM downloader for programming the Xilinx high-density XC4000-Series FPGAs in embedded applications.
