HardWire Arrays

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Xilinx HardWire Arrays complement the flexibility and time-to-market advantage of our programmable FPGA technologies. By providing customers with a transparent, no-risk migration path to dramatic cost reduction without the engineering burden associated with conventional gate array re-design, Xilinx can offer an extremely high production volume solution at a competitive cost.

Download the Xilinx ASIC Estimator to compare product development costs between Xilinx FPGAs, Hardwire Arrays, and Gate Array ASIC Solutions.

Overview
1996 Databook HardWire Chapter
HardWire Forms - Print and submit to Xilinx Product Marketing with the design file and a schematic when submitting the code for conversion to HardWire.
New Design Checklist
Track each milestone in the conversion.
Initial Design Submittal Form
Submits Xilinx FPGA designs for conversion.
Design Verification Forms start prototype production after design review has been approved.

Custom Mark Request Form
Send with Design Verification Forms only when more than one line of custom marking is required.
Additional Prototype and Pre-Production Release Authorization Form
Send with Design Verification Form (when required).
Prototype Approval Form
Approves prototype and starts production.

Programmable elements of the FPGA are removed in the HardWire LCA resulting in a significantly smaller and lower cost die as illustrated above for an XC3000 series HardWire conversion. Functionality is precisely maintained.