Fully
Compliant PCI Interface in an XC3164A FPGA (171kB)
A PCI Target interface implemented in a Xilinx XC3100A-2
FPGA device. VIEWlogic schematics and Verilog source code are available.
The Verilog source has been optimized for use with Exemplar Logic's CORE
logic synthesis software.
Implementing
FIFOs in XC4000E RAM (1226kB)
This Application Note demonstrates how to use the new RAM modes in the
XC4000E logic block. A PCI
Write FIFO is implemented in several different ways, using various combinations
of asynchronous and synchronous, level-sensitive and edge-triggered, single-port
and dual-port RAM.