Asyn and SoftWire

ACEO Technology, Inc.
48834 Kato Road, #105A
Fremont, CA 94538-7368
Tel: 1-510-656-2189
Fax: 1-510-770-9937
info@aceo.com
http://www.aceo.com

Asyn

Asyn provides VHDL and Verilog logic synthesis that is 100% model compatible (language subset and compiler directives) with leading synthesis tools. Asyn optimizes logic for ASIC and FPGA (CLB optimization for Xilinx) and for area cost and timing performance; supports design hierarchy, mixed HDL and gage (netlist) input, and mixed HDL languages (Verilog and VHDL).

Asyn is tightly integrated into all VIEWlogic design environments with an intuitive graphical user interface, and other major EDA platforms. Combined with ACEO's SoftWire for multi-FPGA partitioning, the two form the most complete high-level FPGA design solution on PC/Windows and workstations.

Product Highlights

• Fully model compatible with leading synthesis tools
• Large capacity (150K+ gates), very fast run time, competitive results
• Optional HDL signal name preservation; ideal for design prototyping
• Mixed inputs (HDL and gates), mixed languages (VHDL and Verilog)
• Supports PC/Windows and Sun; all Xilinx FPGAs (XC3000, XC4000, and XC5000)

Xilinx-Specific Highlights

• Optimization of CLB and IOB structures for all Xilinx FPGAs
• Back-annotation of post-layout timing directly from XACT using XNF
• Automatic pad insertion and mapping to X-BLOX functions
• Forward passing of timing constraints to XACT
• XNF to VHDL or Verilog netlist creation for pre- or post-layout simulation

Design Flow

1. Describe your design in VHDL or Verilog
2. Perform functional simulation of your HDL design
3. Use Asyn to synthesize your HDL design into an optimized XNF netlist
4. Run XACT on XNF for Xilinx place and route
5. Optionally, take post-layout XNF to Asyn for back-annotation and a full timing report on critical paths and constraint status

SoftWire

SoftWire supports FPGA product design and offers multi-FPGA partitioning. Gatran offers netlist technology mapping from ASIC to FPGA. SoftWire and Gatran together support rapid ASIC prototyping using FPGAs by transforming an ASIC design into a design consisting of multiple FPGAs.

Design mapping is FPGA-architecture specific and partitioning is cost or time driven, automatic or manual. SoftWire offers plenty of partitioning control including engineering change orders (ECOs) for easy design iteration. Both products are tightly integrated into all Viewlogic design environments and other major EDA platforms. SoftWire and Gatran, together with ACEO's Asyn logic synthesis tools, form the most complete high-level FPGA design solution on PC/Windows and workstations.

Product Highlights

• Multi-FPGA partitioning and optional design mapping from ASIC to FPGA
• Partitioning for custom and programmable PCBs, with programmable interconnects
• Incremental partitioning for easy design change
• Very large gate count (150K+ gates) and fast run time
• Supports PC/Windows and Sun; all Xilinx FPGAs (XC3000, XC4000, and XC5000)

Xilinx-Specific Highlights

• CLB-based mapping algorithms from ASIC to Xilinx FPGAs
• CLB-based multiple Xilinx FPGA partitioning with accurate and aggressive results
• Automatic synthesis of non-implementable ASIC logic into Xilinx logic structures
• Automated interface with XACT for multiple FPGAs * Plenty of Xilinx partitioning control: utilization, logic and pin assignment, etc.