Design Works
Capilano Computing
960 Quayside Drive #406
New Westminster, BC V3M6G2 Canada
Tel: 1-702-456-1222
Fax: 1-702-456-1310
Order: 1-800-487-8743
Tech: 1-800-499-6867
DesignWorks is an integrated schematic entry and digital logic simulation
package with a wide variety of interfaces and design kits for PCB and FPGA
design. DesignWorks features an advanced schematic editor with full hierarchical
design, bussing, multi-page drawings, integrated symbol editor, design
error checking, Cut/Copy/Paste, rubber banding, etc.
Powerful text attribute support allows all your design data to be kept
with the schematic, including FPGA or PCB layout parameters, simulation
data, etc. In addition, DesignWorks features a unique, completely interactive
simulation which presents a ""live"" circuit on the
screen.
Product Highlights
- Supports board-level, PLD and FPGA design.
- Numerous industry-standard netlists plus Verilog and VHDL.
- EDIF 2 0 0 full schematic in and out.
- Extensive symbol and simulation model libraries.
- Available for Windows 3.1/95/NT and Apple Macintosh.
Xilinx-Specific Highlights
- Create schematics using the standard Xilinx Unified Libraries.
- XNF netlist output and post-layout back annotation.
- Simulate the complete Xilinx design before and after layout.
- Incorporate PLA devices into the design.
- CLB assignment, device/speed grade, etc. on the schematic.
Design Flow
Xilinx design creation with DesignWorks consists of the following steps:
- Create a schematic diagram using symbols from the Xilinx Unified Libraries.
Libraries contain full-functional simulation models.
- Enable the DesignWorks Simulator and perform a functional simulation
(unit delay). Make any design modifications necessary, even while the simulator
is running. There is no netlist generation and no switching between applications.
- Generate the XNF netlist file and run the XACT place and route software.
- Back-annotate post-layout delays and re-run simulation to verify timing
performance.
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