Galileo
Exemplar Logic, Inc.
815 Atlantic Avenue, Suite 105
Alameda, CA 94501-2274 U.S.A.
Tel: 1-510-337-3700
Fax: 1-510-337-3799
info@exemplar.com
http://www.exemplar.com
Only Exemplar Logic has a tool for every level of designer and a migration
path from beginner to expert. VHDL Discovery Kit is for ""second-wave""
designers who wish to learn VHDL synthesis with an experienced leader in
FPGA synthesis. The VHDL Discovery Kit features Esperan MasterClass Multimedia
VHDL Tutorial, a Galileo-based synthesis engine, and your choice of one
FPGA technology library.
Galileo is an integrated user environment for synthesis, timing verification
and simulation of FPGAs and ASIC designs. Galileo can be purchased as either
a point tool or in various bundles as a complete tool suite.
Leonardo is for advanced, interactive, hierarchical design and verification
of high density FPGAs and ASICs. Leonardo goes beyond Galileo to open up
the synthesis design environment so that users have control and visibility
through each step of their design process. Users can synthesize different
portions of their design differently, based on their requirements.
The Exemplar Advantage - Exemplar Logic has over 9 years of experience
in Xilinx-specific optimization. Exemplar offers a complete high level
design environment including synthesis, timing analysis, and VITAL backannotation
to simulation for PC, Sun, or HP platforms. Exemplar supports all major
Xilinx technologies and was the first to support VITAL backannotation to
simulation for Xilinx with Exemplar-developed VITAL libraries.
Product Highlights
- Easy-to-use graphical interface
- Module generation for structured logic synthesis and design re-use
- Technology-specific optimization algorithms take advantage of device
features for improved area/speed performance
- Hierarchy support
- Netlist retargeting capability
- Leading-edge VHDL/Verilog support with the broadest coverage in the
industry
- Multi-platform support: PC (Windows 95 and NT), Sun, and HP
- Comprehensive error checking and reporting
- Timing analysis
- Schematic viewing
- VITAL backannotation
Xilinx-Specific Highlights
- Modgen support of arithmetic and logic operators (RAMs, counters, adders,
incrementers, shifters, etc.)
- Modgen uses Xilinx-specific structures such as fast carry chains
- Automatic use of clock enable on DFFs
- Look-up table (LUT) mapping algorithms map directly to FMAP and HMAP
symbols
- Automatic detection of GSRs
- Complex I/O mapping
- TimeSpec support through XNF
- Use of special cells, such as boundary scan, RAM, startup block and
edge decoders
- Automatic use of IOB registered logic
- Using other Xilinx attributes, such as pin number and location
- User choice of state machine encoding
- Support for XBLOX modules from Module Generation
- Support for mixed HDL/schematic design entry
- Constraint-driven timing optimization
- CLB packing (for XC4000)
- Write XNF primitives or EQN symbols
- Full backannotation support through VITAL models
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