Fujitsu

---

PROVERD

Fujitsu LSI Technology Limited
KSP R&D A3F
3-2-1, Sakado Takatsu-Ku, Kawasaki 213,
Japan
Tel: 81-44-812-8065
Fax: 81-44-812-8066

PROVERD (Professional Verilog Design System) is a top-down design system for ASICs and FPGAs. PROVERD features a mixed-mode design entry tool (schematic and VerilogHDL), a high-speed simulator based on OVI/LRM (Open Verilog International/Language Reference Manual), and many standard interfaces including VerilogHDL, EDIF and TSSI-WGL (Test Systems Strategies Inc. -Wave form Generation Language). PROVERD operates in Windows 3.1, which enables users to construct the design tools in their own environments.

Product Highlights

• Supports hierarchical schematic entry, VerilogHDL, and gate-level simulation for Xilinx devices
• Operates on PC-AT and compatibles including NEC PC-98xx and Fujitsu FMR series running Windows 3.1
• Supports Xilinx XC3000 and XC4000 devices, and X-BLOX

Xilinx-Specific Highlights

• Creates parameterized schematics with X-BLOX symbols
• Outputs XNF netlist
• Back annotates post-layout timing from XACT¨ via XNF interface
• Converts XNF to VerilogHDL

Design Flow

1. Create a hierarchical design for your Xilinx device using symbols for Xilinx (just like Unified Libraries).
2. Generate a Xilinx netlist for transfer to Xilinx XACTstep software.
3. Run the XACTstep place and route software.
4. Back annotate post-layout delays and simulate to verify timing performance.

© 1996 Xilinx, Inc. All rights reserved
Trademarks and Patents