OrCAD FPGA Designer

OrCAD Direct
9300 S.W. Nimbus Avenue
Beaverton, OR 97008-7137 U.S.A.
Tel: 1-800-671-9505
Tel: 1-503-671-9500
Fax: 1-503-671-9501
info@orcad.com
http://www.orcad.com

OrCAD FPGA Designer is a comprehensive design entry and debugging tool set for designing complex PLDs or FPGAs. OrCAD Capture and OrCAD Simulate are components of FPGA Designer. OrCAD Capture provides an easy-to-use hierarchical schematic editor and design manager to create structural designs of any complexity. OrCAD Simulate is a full-featured gate-level simulator designed to make functional, timing, and system-level simulation of PLDs easier and faster.

Tight integration with Xilinx XACTstep software lets you create the required XNF netlist quickly, and then easily back annotate timing delays from your routed design to test performance.

Product Highlights

• 32-bit Windows applications run on Windows 3.1, Windows95, and Windows NT
• Integrated and easy-to-use hierarchical project management and design entry, logic debugging, and timing simulation for all Xilinx FPGA families
• Full support for PCB-level design entry and simulation

Xilinx-Specific Highlights

• Library and model support for Xilinx XC3000, XC4000, XC5200, and XC7000 devices
• Mix schematic logic macros, parameterizable blocks (X-BLOX), and synthesized XNF modules
• Simulates multiple Xilinx LCAs

Design Flow

1. Capture a structural design for your Xilinx device with Xilinx-supplied symbols and schematics.
2. Adjust the data path into X-BLOX parameterized modules. Include XNF modules created by HDL synthesis tools.
3. Simulate early in the design flow by converting a Xilinx netlist into a functional simulation model.
4. Describe circuit stimulus with dialog-based, interactive stimulus or compose a VHDL test bench in the programmer's editor.
5. Display simulation results graphically as waveforms, text listing as a truth table, or directly on the schematic.
6. After design capture, import OrCAD netlists into Xilinx XACTstep software.
7. After place and route and timing analysis by the implementation tools, import the Xilinx netlist into Simulate. Timing parameters embedded in the XNF file are extracted to create a timing-based simulation model.
8. Check the performance of the routed design in Simulate. Timing violations are automatically flagged and general logic expressions breakpoints built to assure the LCA will operate correctly in the system.
9. Create a system design of the PCB, which includes multiple PLDs, FPGAs, and standard digital components. Use the interfaces supplied with OrCAD Capture to create a netlist for PCB layout.

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