Motive
A high-performance analysis tool, Quad Design's Motive increases designer productivity by interactively identifying all critical paths and speeding the correction of timing problems. Offering the most accurate representation of interconnect delay for all digital technologies, Motive requires no test vectors, provides improved accuracy using delay data from PDQ, XTK, or ASIC vendor, and accurately analyzes complex synchronous and semi-synchronous designs.
Motive identifies all setup and hold violations in a design by exhaustively tracing every signal delay path. Accounting for worst case (minimum/maximum) interconnect and component delays, Motive provides comprehensive timing analysis on designs ranging from ASICs to systems.
As a timing analysis tool, Motive has the ability to operate from either a schematic capture netlist or post route information. Driving Motive from the netlist allows the user to identify the critical traces for placement and routing. This leads to a higher quality route the first time. Driving Motive from the post route information, namely the XNF file, provides the user with a view of routing-based issues. Typical examples are clock skew or the design not meeting a required operating frequency.
Motive requires three inputs: the netlist, a clock definition, and a model file. Optionally, the interconnect data may be supplied. The outputs are timing violation reports, both text and graphics, and a prioritized critical net report.
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