The SILOS III Simulation Environment is the latest advancement in Verilog HDL-based digital simulation technology. SILOS III is the only HDL simulator offering interactive logic and fault simulation at all levels of abstraction.
Verilog HDL is fully supported at the behavioral, gate, and switch levels. There is even support for the new analog behavioral modeling extensions. SILOS III delivers the performance of a compiled technology simulator while retaining the debugging attributes of a high speed interpreted simulator.
SILOS III's performance, even on a PC, will rival the competition's workstation-based simulators, thus providing a significant price-to-performance advantage for your hardware and software investment. Whether your design environment is PC or UNIX workstation, SILOS III's superior performance, memory utilization, and outstanding capabilities can address all of your logic and fault simulation requirements.
After design entry, simulation may be used to functionally verify logic. This saves design time because logic errors can be detected and corrected prior to final placement and routing. After a circuit has been placed, routed, and fully debugged using in-circuit emulation, worst-case timing may be verified. This enables the user to select the correct FPGA speed grade for a particular application.
Simulation netlist inputs for FPGA designs are automatically created by the XNF2SILO utility. The network includes logic and routing-delay parameters, and set-up and hold times based upon the selected speed grade operating under worst-case conditions. Simulation stimuli are created with a set of clock statements or with an input pattern for either pad inputs or internal nodes. Simulation results are available in tabular, plotted and graphical formats. This flexibility makes the ""logic debug"" easy for both the circuit function and timing.