Visual HDL
Visual HDL is a high-level system design entry application for ASIC and FPGA design. With Visual HDL, designers can capture their design using easy-to-use and intuitive graphical editors (block diagrams, state machines, flowcharts, algorithmic state machines and truth tables), as well as VHDL's or Verilog text. Then the designer can use Visual HDL's simulation analysis environment to rapidly verify functionality and, if necessary, quickly perform design iterations. Once the designer has verified that the functionality is correct, Visual HDL automatically generates synthesizable VHDL or Verilog code targeted to specific synthesis tools, or EDIF for FPGA design environments.
Visual HDL is used to graphically capture the structure and functionality of the FPGA design. The designer can then use the VHDL simulator built into Visual HDL or use MTT's V-System or Cadence's Leapfrog to verify the functionality of the design. After the design functionality is met, the user can automatically generate VHDL or Verilog code targeted to any one of Visual's supported synthesis vendors, or they can output the design in EDIF if the user wishes to go directly into the Xilinx environment.
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