FREE! Download FPGA Express(TM) evaluation software from the web today. Simply fill out a short registration form and download FPGA Express evaluation software. This software is full featured FPGA Express v1.1 software with support for the Xilinx XC3K, XC4K, and XC5K families of FPGAs, limited to designs up to approximately 1,000 gates. Download today!

FPGA Compiler

Synopsys, Inc.
700 East Middlefield Road
Mountain View, CA 94043-4033 U.S.A.
Tel: 1-415-962-5000
Fax: 1-415-965-8637
designinfo@synopsys.com
http://www.synopsys.com

Synopsys, Inc. develops, markets and supports high-level design automation models and software for designers of integrated circuits (ICs) and electronic systems. The company pioneered the commercial development of synthesis technology, which serves as the foundation of the company's high-level design methodology. Synopsis offers a comprehensive set of synthesis, simulation, test and design reuse solutions, which support both Verilog=AE HDL and VHDL.

Synopsys' mission is to revolutionize the way in which electronic design is done and deliver the new methodologies, tools, and offers a complete line of the productivity of its customers. The company offers a complete line of high-level design tools, including logic and behavioral synthesis, verification, and test; design reuse solutions including the models for high-level system and integrated circuit (IC) design; the Silicon Architects' Cell-Based Array (CBA) and associated tools to optimize designs for minimum silicon area and maximum performance; and customer services.

Product Highlights

• Provides high-level design methodology addressing reduced time-to- market needs of FPGA designers
• Enables rapid FPGA prototyping with a transparent migration path to ASICs
• Synthesizes from industry-standard VHDL and Verilog HDL input

Xilinx-Specific Highlights

• Supports Xilinx XC3000/A, XC3100, XC4000/E, XC4000/EX, XC5200, XC6200, XC7000, and XC9500
• Optimizes Xilinx XC4000 CLB and IOB structures and lookup tables for
• XC3000 and XC5000
• Annotates synthesis timing contraints forward to XACTstep via XNF interface

Design Flow

First, specify your design in VHDL or Verilog. Then, verify the description functionality using Synopsys' VHDL System Simulator (VSS). Once validated, FPGA Compiler synthesizes the design into a FPGA netlist. It optimizes the CLB and IOB structures and the clock enable logic of the XC4000 family, or lookup tables for other families, to render high performance, area-efficient designs. FPGA Compiler also uses the arithmetic logic of the architecture through automatic inferenceing of X-BLOX functions. To maximize device performance and routing efficiency, FPGA Compiler passes timing contraints to the Xilinx XACTstep software. Post-layout timing data may be imported into FPGA Compiler for static timing analysis to verify that the design meets timing constraints and into VSS for dynamic gate-level simulation with full timing prior to device programming.