Synplify

Synplicity, Inc.
465 Fairchild Drive, Suite 115
Mountain View, CA 94043 U.S.A.
Tel: 1-415-961-4962
Fax: 1-415-961-4974
info@synplicity.com
http://www.synplicity.com

Synplicity is the leader in fast, high quality logic synthesis with ""push button"" tool operation. Synplify is the preferred Verilog and VHDL synthesis solution for FPGA and CPLD designers worldwide. Synplify synthesizes Verilog and VHDL designs into small, high performance XNF netlists for Xilinx devices using special optimization, mapping, and module generation techniques. Synplify runs up to 100 times faster than other synthesis tools, and includes the Synplify Editor with synthesis checker to highlight problems for fast design development.

Synplify runs on Sun and HP workstations, and PCs using the Windows 3.1, Windows95, or Windows NT operating system.

Product Highlights

• Runs up to 100 times faster than other synthesis tools
• Comes with the Synplify Editor, an integrated HDL design entry tool
• Supports synthesizable IEEE 1076-1993 and 1164 VHDL, and IEEE 1364 Verilog
• Supports the major Xilinx device families
• Runs on Suns and HPs and PCs

Xilinx-Specific Highlights

• Maps directly to Xilinx's FMAPS, HMAPS, AND X-BLOX
• Uses proprietary DST (Direct Synthesis Technology), bypassing
• X-BLOX for XC4000
• Infers counters, adders, subtractors, etc., and performs module generation
• Automatically uses the flip-flop load enable, GSR, and clock buffer resources
• Automatically inserts I/Os and uses the flip-flops in I/Os as appropriate
• Cleanly supports instantiating library primitives and black boxes

Design Flow

Create your VHDL or Verilog Design. You can use one of many examples provided as basis for your design. Don't forget to perform a syntax and synthesis check in the Synplify Editor. Synplify will highlight any errors in your code so you can get the bugs out quickly. After you correct any problems, check the logical correctness of your design with a logic simulator. In Synplify, give your source file name, your target device, and click the RUN button to synthesize your design. Synplify will generate an XNF file that contains your optimized design netlist for Xilinx. Run Xilinx XACT to place and route, and program your part. XACT will generate a timing-annotated XNF netlist to read into your logic simulator so that you can perform a final functional simulation after place and route.

For a presentation and demonstration of the Synplify software, as well as the opportunity to load the Synplify software, click Demonstration.

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