Veda Design Automation

VHDLCover, VeriSure, Verdict, VFS

Veda Design Automation
2041 Mission College Blvd., Suite 259
Santa Clara, CA 95054 U.S.A.
Tel: 1-408-496-4516
Fax: 1-408-496-4521
support@usveda.com

Veda's strategy is to address the testing issue starting at the high level design stages and proceeding through with gate level fault simulation.

VHDLCover and VeriSure offer the ability to quantify how well the testing has progressed prior to the synthesis step. VHDLCover performs this high level analysis for VHDL based designs and VeriSure performs this analysis for Verilog based designs.

For fault simulation, Verdict provides a fault simulation based solution completely within the VHDL design environment. Verdict supports VITAL libraries and VHDL test benches therefore there is no need to integrate inconsistent tools within the VHDL design environment.

VFS is Veda's offering for a verilog fault simulator. VFS is a high performance, very high capacity fault simulation tool for Verilog designers.

Product Highlights

VeriSure

Ability to perform high level analysis for Verilog designs prior to synthesis
Analysis include statement, branch, conditional, path and variable tracing coverage

VHDLCover

Ability to perform high level analysis for VHDL designs prior to synthesis
Analysis include statement, branch, conditional, path, process and variable tracing coverage

Verdict

Complete VITAL compliant fault simulation all within a VHDL design environment

VFS

High performance, high capacity fault simulator within a Verilog design environment

Xilinx-Specific Highlights

Verdict supports all Xilinx VITAL libraries for a complete fault simulation within VHDL.
VFS supports Verilog gate level libraries providing a complete fault simulation environment for Verilog based designs.