VeriBest

VeriBest, Inc.
6106 Lookout Rd., Suite A
Boulder, CO 80301.
Tel: 1-303-581-9577
http://www/veribest.com
info@veribest.com

VeriBest, Inc. offers design solutions for high-performance, complex circuitry for ASICs, FPGAs, and systems design. VeriBest's tools support the interoperability of Windows 3.1, Windows NT, and UNIX.

Available products include graphical methodology management, process flow management, mixed-level design capture, state diagram design capture and debugging, automatic HDL generation, synthesis, high-performance simulation, and waveform viewing. AdvanSim and VeriBest simulators are VeriBest's VHDL and Verilog simulation environments. Personal VeriBest Designer offers a complete Verilog HDL solution on Windows 3.1. Xilinx Design kits are available for all platforms and simulators.

Product Highlights

• Pre- and post-layout performance simulation including pre-layout
• X-BLOX
• Mixed-level design capture and automatic HDL generation
• Synthesis tools feature full chip timing optimization and technology mapping
• Database compatible across UNIX, Windows NT and Windows 3.1 platforms

Xilinx-Specific Highlights

• Supports XC3000, XC4000 FPGAs, and X-BLOX (XC5000 support will be available with XACTstep 6.0/5.2)
• Pre-layout simulation of X-BLOX does not require X-BLOX processing
• Xilinx Netlist Format (XNF) to Verilog/SDF converter
• Single, streamlined work flow for all libraries
• Package-level support for many Xilinx device packages

Design Flow

After capturing the textual and graphical mixed-level design, pre-layout simulation can be performed to ensure that the design is functionally correct. A Xilinx netlist is generated for transfer to the Xilinx XACTstep tools. The back-annotated output can be simulated using the Standard Delay Format (SDF) for post-layout simulation.

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