EDA Diamond Partners Product Table

CompName

ProdName

Ver.

Function

DesignKit

3k/4k

5k

7k/9k

UniLib

PC

Sun

RS6000

HP7
Aldec Active-CAD

2.2

Schematic Entry, State Machine & HDL Editor, FPGA Synthesis, and Simulation Included

-

-

-

Cadence Verilog

2.4

Simulation Xilinx Front End

7k

-

Concept

2.1

Schematic Entry Xilinx Front End

-

7k

-

FPGA Designer

9504

Topdown FPGA Synthesis Call Xilinx

7k

-

Synergy

2.3

FPGA Synthesis Call Xilinx

7k

-

Composer

4.4

Schematic Entry Xilinx Front End

-

7k

-

Mentor Graphics Autologic

A.3-B.1

 Synthesis Xilinx Synthesis Library

-

Galileo

3.2.5

 Synthesis/Timing Analysis Call Mentor

-

Leonardo

4.01

 Synthesis/Timing Analysis Call Mentor

-

Design Architect

B.x

Schematic Entry Call Xilinx

-

QuickSim II

B.x

Simulation Call Xilinx

-

QuickHDL

B.x

HDL Simulaton Call Xilinx

-

OrCAD Capture (Win)

7.0

Schematic Entry Call OrCAD

-

-

-
Simulate (Win)

6.10

Simulation Call OrCAD

-

-

-
VST 386+ (DOS)

1.2

Simulation Call OrCAD

-

-

-

-

-

SDT 386+ (DOS)

1.2

Schematic Entry Call OrCAD

-

-

-

-

-
PLD 386+ (DOS)

2.0

Synthesis Call OrCAD

-

-

-

-

-

Synario Design Automation ABEL

6.3

 Synthesis, Simulation ABEL-XCPLD

-

-

-

-

Synario

2.3

Schematic Entry, Synthesis & Simulation SYN-LCA, SYN-XCPLD

-

-

-

Synopsys FPGA Express

1.1

 Synthesis Call Synopsys

9k

June

-

-

-

FPGA Compiler

97.01

 Synthesis Call Xilinx

-

Design Compiler

97.01

 Synthesis Call Xilinx

-

VSS

97.01

 Simulation Call Xilinx

-

VIEWlogic WorkView Office

7.1.2, 7.2

 Schem/Sim/Synth Call Xilinx

-

-

-

ProSynthesis

5.02

Synthesis Call Xilinx

7k

ProSim

6.1

Simulation, Timing Analysis Call Xilinx

7k

ProCapture

6.1

Schematic Entry Call Xilinx

7k

PowerView

6.0

Schem/Sim/Synth/Timing Anal Call Xilinx

-