EDA Emerald Partners Product Table

CompName

ProdName

Ver

Function

DesignKit

3k/4k

7k/9k

UniLib

PC

Sun

RS6000

HP7
Accolade Design Automation PeakVHDL

3.2

 Simulation Included

-

-

-

PeakFPGA

3.20

 Synthesis Included

-

-

-

ACEO Technology Asyn

4.1

 Synthesis Included

-

Softwire

3.3

Multi-FPGA Partitioning Included

-

Gatran

3.3

ASIC to FPGA Netlist Mapping Included

-

Acugen Software Sharpeye

2.60

 Testability Analysis AALCA interface

7k

-

-

. ATGEN

2.60

Automatic Test Generation AALCA interface

7k

-

-

AAFSIM

2.60

Fault Simulation AALCA interface

7k

-

-

PROGBSDL

2.63

BSDL Customization AALCA interface

7k

-

-

TESTBSDL

2.63

Boundary Scan ATG AALCA interface

7k

-

-

ALPS LSI Technologies Edway Design Systems

-

 Synthesis/Simlulation

-

-

-

-

-
Aptix Corporation System Explorer

3.1

 System Emulation Axess 3.1

-

-

-

ASIC Explorer

2.3

ASIC Emulation Axess 2.3

4K

-

-

-

-

-
Aster Ingenierie S.A. XILLAS

4.2

 LASAR model generation Worst Case Simulation

7k

-

-

Auspy Development APS

1.3.3

 Multi-FPGA Partitioning Included

-

-

-
Chronology Corporation TimingDesigner

3.0

 Timing Specification and Analysis Included

-

QuickBench

1.0

Visual Test Bench Generator Included

-

CINA SmartViewer

1.0e

Schematic XNF Interface

7k

-

-

-

-
Epsilon Logic Compressor

-

 Synthesis

-

-

-

-

-

-
Flynn Systems Probe

3.0

Testability Analysis Xilinx Kit

7k

-

-

-

-
FS-ATG

3.0

Test Vector Generation Xilinx Kit

7k

-

-

-

-
CKTSIM

3.0

Logic Analysis Xilinx Kit

7k

-

-

-

-
FS-SIM

3.0

Simulation Xilinx Kit

7k

-

-

-

-
Fujitsu LSI PROVERD

-

Top-Down Design System Included

-

-

-

-

-
Harmonix PARTHENON

2.3

 Synthesis

-

4k

7k

-

-

-

Logical Devices Total Designer

4.7

 Simulation & Synthesis Call Xilinx

-

-

-

Ulysa

1.0

VHDL Synthesis Call Xilinx

-

-

-
MINC PLDesigner-XL/ PLSynthesizer

3.3/ 3.2.2

 Synthesis Xilinx Design Module

-

-

-

MicroSim MicroSim DesignLab

-

Schematic Entry, Mixed A/D & FPGA Simulation, PCB Layout and Routing included Included

-

-

-

-
Teradyne Lasar

6

Simulation Xilinx I/F Kit

-

-

-

-

Tokyo Electron Limited ViewCAD

1.2

 FLDL to XNF translator XNFGEN

-

-

-

-

-

-

Trans EDA Limited TransPRO

1.2

 Synthesis Xilinx Library

-

-

-

-

Visual Software Solutions Statecad

3.0

 Graphical Design Entry/Simulation/Debug

-

-

Zuken Tsutsuji

-

Synthesis/Simulation XNF Interface

-

-

-

Zycad Paradigm RP

-

Rapid Prototyping

-

-

-

-

-

Paradigm XP

-

Gate-level Sim

-

-

-

-

-