
| CompName |
ProdName |
Ver |
Function |
DesignKit |
3k/4k |
7k/9k |
UniLib |
PC |
Sun |
RS6000 |
HP7 |
| Capilano Computing | Design Works |
3.1 |
Schematic Entry/Sim | XD-1 |
|
- |
|
|
- |
- |
- |
| Compass Design Automation | ASIC Navigator |
- |
Schematic Entry | Xilinx Design Kit |
|
7k |
- |
- |
|
- |
|
| X-Syn |
- |
Synthesis | - |
|
- |
- |
- |
|
- |
|
|
| QSim |
- |
Simulation | - |
|
7k |
- |
- |
|
- |
|
|
| Escalade | DesignBook |
2.0 |
Design Entry | - |
|
- |
|
|
|
- |
- |
| Exemplar | Galileo |
3.2 |
Synthesis/Timing Analysis/ Simulation | Included |
|
|
|
|
|
- |
|
| IK Technology | ISHIZUE PROFESSIONALS |
1.06 |
Schematic Entry/Simulation | Xilinx Design Kit |
|
- |
- |
|
|
- |
|
| IKOS Systems | Voyager |
2.31 |
Simulation | Xilinx Tool Kit |
|
- |
- |
- |
|
- |
|
| Gemini |
1.21 |
Simulation | Xilinx Tool Kit |
|
- |
- |
- |
|
- |
|
|
| INCASES Engineering GmbH | Theda |
5.0 |
Design Entry | Xilinx Kit |
|
- |
- |
|
|
|
|
| ISDATA | LOG/iC2 |
5.0 |
Schematic, Synthesis, Simulation | Xilinx Mapper |
|
|
|
|
- |
- |
- |
| Logic Modeling (Synopsis Division) | Smart Model |
- |
Simulation Models | In Smart Model Libary |
|
|
- |
|
|
|
|
| LM1200 |
- |
Hardware Modeler | Xilinx Logic Module |
|
|
- |
|
|
|
|
|
| Model Technology | V-System/VHDL |
4.4j (PC) 4.6a (WS) |
Simulation | - |
|
- |
|
|
|
|
|
| Protel Technology | Advanced Schematic |
3.2 |
Schematic Entry | Included |
|
7k |
|
|
- |
- |
- |
| Advanced PLD |
3 |
PLD/FPGA Design & Simulation | Included |
|
7k |
- |
|
- |
- |
- |
|
| Quad Design Technology | Motive |
4.3 |
Timing Analysis | XNF2MTV |
|
- |
- |
|
|
|
|
| SimuCad | Silos III |
96.1 |
Schematic Entry & Simulation | Included |
|
- |
|
|
- |
- |
- |
| Sophia Sys & Tech | Vanguard |
5.31 |
Schematic Entry | Xilinx I/F Kit |
|
|
- |
|
|
- |
|
| Summit Design Corporation | Visual HDL |
3.0 |
Graphical Design Entry/Simulation/Debug | EDIF Interface |
|
|
|
|
|
|
|
| Synplicity | Synplify-Lite |
2.6b |
Synthesis | Xilinx Mapper |
|
9k |
|
|
|
- |
|
| Synplify |
2.6b |
Synthesis | included |
|
9k |
|
|
|
- |
|
|
| TopDown Design Solutions | New product information coming soon | ||||||||||
| VEDA Design Automation | Vulcan |
4.5 |
Simulation | XILINX Tool Kit |
|
- |
- |
- |
|
- |
|
| VeriBest | VeriBest VHDL |
14.0 |
Schematic Entry | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
| VeriBest Verilog |
14.0 |
Simulation | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
|
| VeriBest Simulator |
14.0 |
Simulation | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
|
| DMM |
14.x |
Design Management | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
|
| VeriBest Synthesis |
14.0 |
Synthesis | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
|
| Synovation |
12.2 |
Synthesis | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|
|
| PLDSyn |
12.0 |
Design Entry Synthesis | - |
|
7k |
- |
|
|
- |
|
|
| VeriBest Design Capture |
14.x |
Design Capture | Xilinx FPGA Design Kit |
|
- |
|
|
|
- |
|