By extending the density reach of the world's most successful FPGA family, the XC4000, Xilinx has brought the time-to-market and risk reduction benefits of programmable logic further into traditional gate array territory. The XC4000EX Family of FPGAs elevates the XC4000 Series to industry leading densities with devices ranging from 28,000 to 125,000 logic gates. Abundant new routing resources deliver the fast compile times and high completion rates. The innovative VersaRing(tm) I/O interface, comprised of rich routing resources along the edge of the device, maximizes overall utilization and pin locking capability.
Designed from the ground up for speed and density using deep submicron triple layer metal technology, the XC4000EX delivers system performance up to 66 MHz and is 100% PCI compliant. Select-RAM Memory is a Xilinx unique feature that dramatically improves system performance, ease-of-use and overall gate count. This feature allows easy distribution of high performance customized single or dual port RAM functions (FIFOs, accumulators, LIFOs, etc.) into a single FPGA eliminating the costly on/off chip delays of external RAM. For example, a 32 x 16 dual port FIFO can be implemented using 48 CLBs and run at 80 MHz.
The XC4000EX uses an ASIC design flow by offering LogiCore system level design modules, highly efficient synthesis results for Verilog and VHDL designs, and XACTstep development support. Xilinx currently offers fully verified PCI LogiCore modules and will soon be delivering a complete library of functions including popular DSP and telecom algorithms. We have leveraged our extensive 3rd party EDA relationships and are now able to deliver synthesis friendly solutions from 3,000 to 125,000 gates in the XC4000 Series. For high volume applications, mask programmed HardWire versions are available with significantly reduced unit costs.
See the Product Information section for more information on the industry's highest density FPGAs!!
© 1996 Xilinx, Inc. All rights reserved
Trademarks and Patents