Xilinx Product Spotlight : XC9500 ISP CPLDs

New In-System Programmable XC9500 CPLDs -- Leadership Speed, Architecture, Ease-Of-Use

Advanced pin-locking architecture
High performance to 5ns speeds
5V in-system programmable
Complete IEEE 1149.1 (JTAG) support
FastFLASH CPLD technology

A New Leadership In-System Programmable CPLD Family:

From the leader of FPGA technology, the next generation of CPLDs is here! The XC9500 family delivers the ultimate in performance, flexibility, and ease-of-use for your high-performance system logic needs. With fast pin-to-pin speed, performance predictability, and fast compile times, the XC9500 CPLDs are the perfect CPLD companions to Xilinx's leading edge FPGAs.

All XC9500 CPLDs support in-system programmability (ISP) for making changes right on the board, eliminating the need for sockets and minimizing device handling. With ISP, no more bent leads with space-saving PQFP and TQFP packages. To fully support in-system programmability, the XC9500 incorporates special architectural features to enhance pin-locking capability. In addition, all XC9500 devices support full 1149.1 (JTAG) boundary scan, including support for version control and in-system test.

Next Generation Architecture Provides Pin-Locking and Maximum Flexibility:

Pin-locking, the ability to lock user pin assignments during design iterations, is crucial to fully supporting ISP. The XC9500 architecture supports the industry's best pin-locking by providing a 100% connectable interconnect matrix and advanced block-wide product term allocation. When additional logic is added, these features ensure that additional product terms can be allocated, and additional signals routed using the same pin assignments.

The architecture also provides individual output enable signals for each pin, supporting multiple data busses and tri-state controls. Each macrocell can support up to 90 product term functions. This, in conjunction with an abundance of global and product term clocks provide the ultimate in architecture flexibility available today!

Full JTAG Support:

All XC9500 devices support the IEEE 1149.1 boundary-scan standard, including support for built-in version control and in-system debug (via USERCODE and INTEST instructions, respectively). Using the industry-standard 4-pin interface, all in-system programming, design debugging, and boundary-scan is supported.

For more information see the XC9500 Family Datasheet.