Cadence Interface: Glossary

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API body cds_action cds.lib chips_prt (CIB) CIW Composer Concept Concept2xil Concept2xnf

EDIF Genview global.cmd HDL HDL Direct hdlconfig IEEE IEEE 1164 iterated instance logic drawing

M1.x master.local mixed mode design OVI Rapidsim SIR2EDF SIZE SKILL Synergy startup.concept

testbench Unified Library VAN Verilog Verilog-XL VHDL VHSIC VITAL .wrk file X-BLOX

XNF

API

Applications Programming Interface. A set of software libraries, developed by a particular software vendor, that allows 3rd party software programs to interface with programs from that vendor.

body

A Concept symbol. The format of a body file name is body.<version>.<sheet_number>. Example: body.1.1 is version 1, sheet 1 of a Concept symbol.

cds_action = "ignore"

Verilog parameter definition that must be added to the Verilog .v file generated for a LogiBLOX, or other non-schematic block to indicate to Concept2XIL that there are no other underlying levels of hierarchy associated with a given block.

cds.lib

A library mapping file pointing to the VAN-compiled Verilog libraries used by Concept2XIL and Concept.

chips_prt

Concept parts file. Contains physical information about a board level part

CIW

Command Interpreter Window. Startup window for Design Framework and Composer.

Composer

Cadence schematic editor. Used mainly by IC designers.

Concept

Cadence schematic editor used mainly by board level designers. Originally from a company called Valid which was purchased by Cadence.

Concept2xil

Cadence's EDIF netlist writer which interfaces to Xilinx's M1.0 flow. Generates an EDIF netlist from Verilog netlist(s) generated by HDL Direct in Concept.

Concept2XNF

Cadence's XNF netlist writer which interfaces to Xilinx's XACT 5.x flow. Generates an XNF netlist from a Concept schematic using CAEVIEWS.

EDIF

Electronic Design Interchange Format. An industry-standard netlist format.
In the Xilinx M1 flow, EDIF is the standard input format.

Genview

A program that ships with the Cadence Concept schematic editor. Genview generates a symbol body from a Concept schematic, a Verilog netlist, or a user-specified portlist.

global.cmd

Concept setup file containing aliases to the Xilinx and Cadence libraries available for your design.

HDL

Hardware Description Language. A language which describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.

HDL Direct

Cadence Concept methodology for generating simulatable Verilog and VHDL code directly from schematics. Required methodology for Xilinx M1.0 interface.

hdlconfig

Concept HDLConfig traverses a design's hierarchy and generates a design configuration that points to the cellviews for all the blocks in your design. In the 9604 release, HDLConfig reads the global.cmd and hdldirect.dat files.

IEEE (pronounced "I triple-E")

Institute of Electrical and Electronics Engineers.

IEEE 1164 Standard

The IEEE standard for Verilog HDL supported by Open Verilog International. To order a copy of this standard, see: http://standards.ieee.org/catalog/contents.html> under Information Technology, subcategory, "Design Automation".

iterated instance

Concept methodology for replicating bodies which involves adding an index range to the value of the PATH property for a given instance. Use this methodology to replicate bodies in M1.0 instead of the SIZE property.

logic drawing

A Concept schematic. The format of a logic drawing file name is logic..<version>.<sheet_number>. Example: logic.1.2 is version 1, sheet 2 of a Concept schematic.

M1.x

Xilinx Merged Release v1.x. New toolset from Xilinx incorporating XFoundry place and route, low level editor and static timing analyzer. Uses EDIF as the standard input format.

master.local

A SCALD library mapping file which lists the explicit paths to user libraries. Aliases to each user library are defined in this file. Libraries defined in master.local are available to your design if you include a "master_library" directive in your global.cmd pointing to master.local.

mixed mode design

A mixed mode design is one that consists of both schematic and non-schematic blocks.

OVI

Open Verilog International. An organization that exists to promote and support the use of Verilog HDL worldwide. OVI supports the IEEE 1364 standard for Verilog HDL.

Rapidsim

Cadence's discontinued schematic simulator. Also originally developed by Valid . Tightly integrated with Logic Workbench and the Concept schematic editor.

SIR2EDF

SIR2EDF is Cadence's generic SIR (Structural Intermediate Representation) to EDIF conversion tool. Concept2XIL invokes SIR2EDF after running HDLConfig and VAN.

SIZE

Concept property used for replicating symbols. Not supported in Xilinx M1.0 Concept and Verilog libraries--you must use Iterated Instance methodology instead.

SKILL

Cadence's scripting language, used by Design Framework programs such as Composer, and Verilog-XL.

Synergy

Cadence's synthesis engine. Currently (1/97) supports 2K, 3K, 4K, 4KE, 5K, 7K device families. Supported by Cadence.

startup.concept

Concept startup file. Contains commands that set various modes of Concept operation. Commonly used to activate HDL Direct and HDL Direct related checks at startup.

testbench

HDL netlist containing test vectors to drive a simulation.

Unified Library

Xilinx library standard which emphasizes standardization of component naming and physical appearance of all schematic symbols across all FPGA and CPLD architectures.

VAN

Cadence's Verilog Analyzer. Concept2XIL calls VAN as well as HDLConfig and SIR2EDF when it processes a Concept schematic.

Verilog

An industry-standard HDL developed by Cadence Design Systems. Recognizable as a file with a .v extension.

Verilog-XL

Cadence's Verilog HDL simulator.

VHDL

VHSIC Hardware Description Language. An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension.

VHSIC

Very High Speed Integrated Circuit.

VITAL

VHDL Initiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4) that defines standard constructs for simulation modeling, accelerating and improving the performance of VHDL simulators.

.wrk file

SCALD library mapping file for you design. Lists the design blocks in the project directory. Updated by Concept when a new block is created.

X-BLOX

Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool where generic bus-width-independent symbols such as counters, adders, and data registers are used to implement architecture-optimized functions.

XNF

Xilinx Netlist Format. The required input format for XACT 5.X (pre-M1) core tools.