Cadence : Top Solutions

Most Often Requested Solutions

XACT 5.X (XNF flow, Cadence 9404 and later)

Solution 518 - VERILOG: How to perform a timing simulation of a Xilinx design using Verilog-XL
Solution 649 - XNF2CDS / XNF2Verilog: Symbol does not have a corresponding entry in the PIN file
Solution 797 - INSTALL, setup and licensing of Sun4 XACT tools with Solaris-based Cadence software
Solution 1529 - CONCEPT / VERILOG: Concept and Verilog interim solution for doing 9500 designs
Solution 646 - VERILOG-XL: driving GSR, GR, and GTS in Verilog simulation
Solution 806 - Post-synthesis Verilog-XL functional simulation is not supported by FUNCNET(X)
Solution 815 - CONCEPT2XNF 9404, 9502: Problems with GND and VCC symbols in XPADS_HDL library
Pre-XACT 5.X (9403 Cadence and earlier)

Solution 1716 - GXILINX: Using pre-5.0 (9403 or earlier) Cadence interface with XACT 5.X
Solution 1479 - GXILINX: FAST property not translated to XNF file / adding support for User properties
Solution 2018 - XNFMERGE, CONCEPT 9402: ERROR: Cannot find PWR.XNFor GND.XNF / How to connect a pin to VCC or GND