Xilinx Synopsys Interface: Glossary

DESIGN_ANALYZER

EDIF

HDL

IEEE

VHDL

XNF

DESIGN_ANALYZER: Synopsys graphical interface to the synthesis tools..
DC_SHELL: Synopsys UNIX command line interface for entering commands, arguments, and options to the synthesis tools.
SYNLIBS: This program displays onscreen the target and link libraries for the specified part type and speed grade. You can append the output of the Synlibs command to the .synopsys_dc.setup file. Warning: You must list the libraries in your setup file in the order that they appear in the Synlibs output.
VHDLAN: The vhdlan program analyzes a VHDL (.vhd) source file for simulation.
VHDLDBX: The Vhdldbx program is the VHDL Debugger, a graphical interface to the VHDL simulator. Through its dialog box, you can issue simulator commands, view command output, and view source code.
DC2NCF: This program translates a Synopsys DC file to an NCF (Netlist Constraints File) file. The DC file is a Synopsys file containing your design constraints.
EDIF: Electronic Design Interchange Format. An industry-standard netlist format.
HDL: Hardware Description Language. A language which describes circuits in textual code. The two most widely accepted HDLs are VHDL and Verilog.
IEEE (pronounced "I triple-E"): Institute of Electrical and Electronics Engineers.
VERILOG: An industry-standard HDL developed by Cadence Design Systems. Recognizable as a file with a .v extension.
VHDL: VHSIC Hardware Description Language. An industry-standard (IEEE 1076.1) HDL. Recognizable as a file with a .vhd or .vhdl extension.
VHSIC: Very High Speed Integrated Circuit.
VITAL: VHDL Initiative Toward ASIC Libraries. A VHDL-library standard (IEEE 1076.4) that defines standard constructs for simulation modeling, accelerating and improving the performance of VHDL simulators.
X-BLOX: Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool where generic bus-width-independent symbols such as counters, adders, and data registers are used to implement architecture-optimized functions.
XNF: Xilinx Netlist Format.