Solutions Database

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Foundation XVHDL: How to lock down I/O pins

Record #1372

Product Family:  Software

Product Line:  Metamor

Problem Title:
Foundation XVHDL:  How to lock down I/O pins


Problem Description:
The information in this Solution Record assumes the use of XVHDL v2.4 or later.
Please note that this is NOT the version that is included with
Foundation version 6.0.1.  Also, this solution and others like it are
contained in the Foundation Documentation Update Pack.	XVHDL v2.4.4 and
the Documentation Update Pack are available from Xilinx:

(Xilinx File ftp://ftp.xilinx.com/pub/swhelp/foundation/spxv.exe)
(Xilinx File ftp://ftp.xilinx.com/pub/swhelp/foundation/fnddoc1a.exe)


To lock down I/O signals to specific pins on the target device,
use the 'PINNUM' attribute in the VHDL code as shown below.
Either declare the pinnum attribute in the entity, or declare the
Metamor library, in which the pinnum attribute is declared.


Solution 1:

--Example of using the PINNUM attribute:

library IEEE;
use IEEE.std_logic_1164.all;

library METAMOR;
--Package attributes contains declarations of the Metamor
--specific synthesis attributes.
use METAMOR.attributes.all;

entity FLOP is
   port (CLK, DIN, RESET: in std_logic;
	INBUS: in std_logic_vector (3 downto 0);
	DOUT: out std_logic;
	OUTBUS: out std_logic_vector (3 downto 0));

   attribute pinnum of DIN: signal is "p20"; -- lock DIN to p20
   attribute pinnum of INBUS: signal is "p16, p17, p18, p19";
		       -- lock INBUS3 to p16 ... INBUS0 to p19.
end FLOP;

architecture LOCTEST of FLOP is
begin
   process (CLK, RESET)
   begin
      if RESET='1' then --asynchronous RESET active High
	 DOUT <= '0';
      elsif (CLK'event and CLK='1') then  --CLK rising edge
	 DOUT <= DIN;
      end if;
   end process;

   OUTBUS <= not INBUS;

end LOCTEST;



End of Record #1372