Solutions Database

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FPGA Express: How to synthesize a hierarchial design in FPGA Express

Record #1460

Product Family:  Software

Product Line:  Synopsys

Problem Title:
FPGA Express: How to synthesize a hierarchial design in FPGA Express


Problem Description:
FPGA Express can Compile hierarchial or flat VHDL or Verilog designs.


Solution 1:

If the design consists of multiple files, the user
must know which file is the 'top' file.  It is
uncessary for the user to know the overall strucutre.

Once the user knows which file is the 'top',
all the user has to do
is select the top-level .v or top-level .vhdl file in his project, push the 'cre
ate implementation' button, specify
constraints, and then push the 'optimize' button.



Solution 2:

If the design is flat, all the user has to do
is select the .v or .vhdl file in his project, push
the 'create implementation' button, specify
constraints, and then push the 'optimize' button.



End of Record #1460