Solutions Database

---

XNF2CDS/XNF2Verilog: Symbol does not have corresponding entry in the PINfile

Record #649

Product Family:  Software

Product Line:  Cadence

Problem Title:
XNF2CDS/XNF2Verilog: Symbol does not have corresponding entry in the
PINfile



Problem Description:
XNF2CDS/XNF2Verilog Error:   Symbol does not have corresponding entry in the
pin file.

Relevant PROGRAMS:  xcdsprep/x2vprep, xnf2cds/xnf2verilog, timenet/timenetx,
funcnet/funcnetx

This problem will be seen in ALL versions up to release 9504

PLATFORM(s): Sun, HP

ERROR MESSAGE:

	ERROR : The following symbol(s) were found in the design, but do
	not have corresponding entries in the PIN file :

If the problem is with the DFF, you will see something like this:

	     Symbol QOUT_REG<9> (type DFF)
	     Symbol QOUT_REG<8> (type DFF)
	     Symbol QOUT_REG<7> (type DFF)
	     Symbol QOUT_REG<6> (type DFF)

This error can be caused by a variety of things.
Basically it means that XNF2CDS/XNF2Verilog is trying to match
up a particular symbol (say, an AND7) in the input XNF file
with an entry in the Verilog simulation library for that architecture
(3000, 4000E, etc.).

The complete list of library components for a given architecture
and the pins associated with each component is specified
in a family-specific .pin file (xc3000.pin, xc4000.pin, etc.),
located in

      $XACT/data for XNF2VERILOG, and

      $CDS_INST_DIR/share/library/xilinx/data for XNF2CDS.

Often you get the "no corresponding entry in the PIN file" error
when the symbol is not a valid simulation primitive.





Solution 1:

Very often this error is issued when XNF2CDS/XNF2Verilog cannot resolve
certain primitives found in a post-synthesis, prerouted Synopsys XNF file.
The same error can appear in designs with other third party synthesis
tools like Exemplar. The error may also be the result of improperly
processing the netlist (skipping xnf2cds or x2vprep).

Note that both XNF2CDS and XNF2Verilog key off the SCHNM property in a
SYM record of an XNF file.  A SYM record looks something like:

SYM, ss_reg<4>, DFF, SCHNM=FDC, LIBVER=2.0.0
PIN, Q, O, output_net_name
PIN, D, I, d_input_net_name
PIN, C, I, clk_input_net_name
PIN, CLR, I, clr_signal_name
END

This particular example is taken out of a .xff generated by SYN2XNF,
the Synopsys to Xilinx translator.

Upon encountering such a SYM record with a SCHNM of "FDC", both XNF2CDS and
XNF2Verilog will look for a library component named "FDC" in the Verilog
simulation library.  However, since FDC is not a valid Unified library
simulation primitive (it should be FDCE), XNF2CDS/XNF2Verilog will flag
an error about not finding an entry in a the Verilog pin file.

In many cases of this error, an XNF file generated by Synopsys contains
modules like DFF, BUFG_F, AND7, etc., for example, that are not standard
Xilinx Unified library simulation primitives.  These modules may be present
in a pre-route XNF generated by Synopsys or other HDL synthesis tool.  They
are also restored to the XNF file when you run XNFBA as part of the timing
simulation flow on a Synopsys design (i.e., running timenet or timenetx
without  the -x  option).

SOLUTION:

1. Functional simulation:
		
Pre-route, post-synthesis functional simulation of Synopsys designs is
currently not supported by the Verilog interface.  As a workaround, you can
simulate the design after allowing PPR to flatten it,  skipping the routing
stage.	In this case, there will be no routing delay information.  To get a
unit delay simulation, you then run Verilog-XL with a +delay_mode_unit option:

syn2xnf
xnfprep
ppr design route=false placer_effort=1
timenetx design xc4000 -x

verilog  +delay_mode_unit  designt.v  designt.stim

2. Timing simulation

Specify the -x option when running timenet (or timenetx in the ES-Verilog
interface) to skip XNFBA.  Version 5.2.1a of timenetx automatically determines
that a design has been generated using Synopsys by looking for a Synopsys
PROG record in the .xff file for the design, if it resides in the working direct
ory.







Solution 2:

Another common cause of this error is trying to process the XNF file directly
using xnf2cds/xnf2verilog.  Preprocessing by xcdsprep/x2vprep is required.

The easiest thing to do is to process the design using one of the following
scripts, which are included in the interface:


				     DS381	      ES-Verilog
				     ------	      --------
functional simulation:	      funcnet		 funcnetx
timing simulation:	      timenet		 timenetx



End of Record #649