Solutions Database

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Post-synthesis Verilog-XL functional simulation is not supported by FUNCNET/FUNCNETX in Cadence or ES-Verilog interface

Record #806

Product Family:  Software

Product Line:  Cadence

Problem Title:
Post-synthesis Verilog-XL functional simulation is not supported by
FUNCNET/FUNCNETX in Cadence or ES-Verilog interface



Problem Description:
Post-synthesis functional simulation of Synopsys designs is currently not
supported by the 5.1.1 or 5.2.x. ES-Verilog Interface and Libraries, nor
is it supported by the Verilog interface shipped by Cadence (9404
through 9504)

Problems with this flow include resolution of certain symbols found
in a post-synthesis XNF netlist processed by SYN2XNF, including
symbols with SCHNM properties that do not reference Unified library
simulation primitives (FDC, FDP, BUFGP_F, etc.).  For example, SCHNM=FDC
references an FDC flipflop, which is not a valid Unified library simulation
primitive.  The correct Unified primitive would be an FDCE.

Since XNF2CDS and XNF2VERILOG key off the SCHNM property when they
translate the XNF file to Verilog, and the libraries only support
Unified library primitives, the translation will fail.

The second issue is with SYM records that are missing SCHNM properties
completely.  These may arise if Synopsys targets XBLOX modules in the
design for certain functions.  The SYM records for such modules will
lack SCHNM properties altogether. In versions of XNF2CDS and XNF2VERILOG
prior to version 9504-1.30v, this situation would result in a processing
failure.


Solution 1:

The workaround is to run XMAKE -x -n on the design.xnf to generate an XTF
file, then run PPR with placer_effort=1 and route=false options to get a
mapped .LCA file.  Finally run TIMENET or TIMENETX -x to generate the
simulation netlist without running XNFBA, and specify the +delay_mode_unit
when running Verilog-XL to run a unit delay simulation.

xmake -x -n design
ppr design placer_effort=1 route=false
timenet -x design
verilog +delay_mode_unit designt.v designt.stim

Note that it is critical to specify the -x option in TIMENET/TIMENETX
so that XNFBA does not restore the original SCHNM properties.



Solution 2:

If the problem is only with the following components
in the design:

  FDC
  FDP
  IFD
  OFD
  OFDT
  BUFGP_F

You can process the design if you strip out the SCHNM properties
associated with these symbols in the .xff output of SYN2XNF,
since in the absence of SCHNM properties on a SYM record
in the XNF/XFF file, XNF2CDS and XNF2VERILOG 9504-1.30v
or later will resolve the symbol to the correct simulation primitive.

If you choose to pursue this route, you must be sure to explicitly
specify the .xff file out of SYN2XNF after the SCHNM properties have been
stripped out as the input to funcnet.

Example:   funcnet design.xff 4000




End of Record #806