Xilinx Product Strategy
We recognize that our future growth is dependent on the development of new products. Our primary product focus is fourfold: to set a new standard for lower complexity CPLDs, to maintain density/performance leadership with our FPGAs, to give our customers a low-cost migration path for high volume applications with our mask programmable HardWire products, and to support all our product families with easy-to-use, fully automated software.
Faster design verification.
Xilinx FPGAs and CPLDs can be designed and verified much faster than traditional gate arrays. Additionally, there are no non-recurring engineering (NRE) costs, no test vectors to generate and no prototypes to wait for. Design changes without penalties. Because Xilinx devices are software-configured via instant programming, modifications are risk-free and can be made anytime. This adds up to significant cost savings in design and production.
Shortest time-to-market.
With Xilinx programmable logic, your time-to-market is measured in weeks rather than the months required for traditional gate arrays. This can be a critical decision in your device selection. In fact, a study by McKinsey and Company concluded that a six-month delay in getting to market can cost a product one-third of its lifetime profit potential. With a custom gate array, design iterations can easily add this critical six months, and more, to a product schedule.
No-risk cost reduction path.
Once the programmable logic design is finalized, high volume applications can take advantage of the Xilinx HardWire conversion for cost reduction. No simulation files or test vectors are required to complete the conversion. No additional customer engineering is required to convert the FPGA design into a fully tested, completely verified HardWire device.
Acceleration of Time to Market/Volume Chart

| PRODUCT FAMILY OVERVIEW | ||||||||
|
Industry Category |
Product Series | Technology | Ideal Use |
Series Key Features | Product Family |
Max. Logic Gates |
Max. I/O | Voltage |
|
(CPLDs) | XC7000 | EPROM |
PAL Integration Low Cost | 5ns Tpd, 100% Utilization, 24mA drive, 3.3V I/O | XC7300 | 0.4K, 3.8K | 156 | 5V |
| XC9000 | FLASH |
ISP Predictable Fast Pin-to-Pin Speeds |
5V ISP, 5ns Tpd, JTAG, Tolerates Pin-Locking, High Endurance | XC9500 | 0.8K-12.8K | 232 | 5V | |
| XC9500F(1) | 0.8K-2.4K | 108 | 5V | |||||
|
| XC3000 | SRAM |
Low Density High Performance | Internal tri-state buffers | XC3100A | 1.50K-7.5K | 176 | 5V |
| XC3100L | 3.0K-6.0K | 144 | 3V | |||||
| XC4000 | SRAM |
High Density High Performance |
Select-RAMTM Distributed RAM, Dedicated Arithmetic, PCI Compliant, JTAG, Internal 3-State Buffers | XC4000E | 3.0K-25K | 256 | 5V | |
| XC4000EX | 28K-44K | 320 | 5V | |||||
| XC4000L | 5.0K-13K | 192 | 3V | |||||
| XC4000XL | 36K-85K | 448 | 3V | |||||
| XC5000 | SRAM | Low Cost |
VersaRingTM I/O, JTAG, Internal tri-state buffers, Dedicated Arithmetic | XC5200 | 2K-23K | 244 | 5V | |
| XC5200L | 2K-23K | 244 | 3V | |||||
(1) NON-ISP version
© 1996 Xilinx, Inc. All rights reserved
Trademarks and Patents