Xilinx has a programmable logic solution for virtually any CPLD design need, from high-speed PAL integration to those designs requiring real-time hardware changes using in-system programmability (ISP) devices. XC9500 family - The New Standard in ISP ISP is revolutionizing today's system designs by providing programming techniques for designing and developing systems with new, previously unattainable capabilities. This ISP capability is the heart of the new XC9500 family, where designers can easily perform virtually unlimited design iterations during the prototyping phase, extensive system in-board debugging, program and test during manufacturing, and field upgrades. The XC9500 devices provide the flexibility of 5V ISP with fast, guaranteed timing, the industry's best pin-locking architecture, a full JTAG compliant interface and 10,000 program/erase cycles. The XC9500 family, with its advanced architecture, is fast becoming the new standard for all ISP CPLDs by providing new levels of features and flexibility for today's system designers.

Advanced 5V ISP CPLDs XC9500 Family High Performance     - 5ns pin-to-pin speeds      - 125 MHz maximum counter frequency High Density 36 to 576 macrocls Industry's best pin-locking architecture 10,000 program/erase cycles Most complete IEEE 1149.1 JTAG Lowest Cost CPLDs XC7300 Family High Performance      -5ns pin-to-pin speeds      -167 MHz maximum counter frequency 100% Interconnect 3.3V/5V I/Os

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