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CPLD Product Selection Matrix
DEVICES
KEY FEATURES
Density
Features
Useable Gates
Macrocells
Flip-Flops
Max. I/O
ISP
Pin-to-Pin Delay (ns)
Output Drive (mA)
PCI I/O
Dedicated Arithmetic
JTAG (IEEE1149.1)
X
C
9
5
0
0
 XC9536 5V ISP
Best Pin-Locking
JTAG
High Endurance 		0.8K 36 36 34 X 5 24 X - X
XC9572 1.6K 72 72 72 X 7.5 24 X - X
XC95108 2.4K 108 108 108 X 7.5 24 X - X
XC95144 3.2K 144 144 133 X 7.5 24 X - X
XC95180 4.0K 180 180 166 X 10 24 X - X
XC95216 4.8K 216 216 166 X 10 24 X - X
XC95288 6.4K 288 288 192 X 10 24 X - X
XC95432(1) 9.6K 432 432 232 X 10 24 X - X
XC95576(1) 12.8K 576 576 232 X 12 24 X - X
XC9536F Non-ISP
Best Pin-Locking
High Endurance 		0.8K 36 36 34 - 5 24 X - -
XC9572F 1.6K 72 72 72 - 7.5 24 X - -
XC95108F 2.4K 108 108 108 - 7.5 24 X - -
X
C
7
3
0
0
 XC7318 100%
Utilization
5ns Tpd
3.3V/5V I/O 		0.4K 18 18 38 - 5 24 X - -
XC7336 0.8K 36 36 38 - 5 24 X - -
XC7336Q 0.8K 36 36 38 - 10 24 X - -
XC7354 1.5K 54 108 58 - 7.5 24 X X -
XC7372 1.9K 72 126 84 - 7.5 24 X X -
XC73108 3.0K 108 198 120 - 7.5 24 X X -
XC73144 3.8K 144 276 156 - 7.5 24 - - -


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