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By providing a complete turn-key conversion service, the engineering burden normally associated with conventional gate array redesign is eliminated.

HardWire cost reduction benefits can be dramatic. The HardWire Gate Array is functionally equivalent and pin-for-pin compatible with the FPGA, but with a smaller die size and significantly lower cost. The combination of FPGA and HardWire makes sense for even the highest volume applications where time-to-market is critical.

Optimized for No Risk Migration

Xilinx has been committed to helping customers achieve cost reduction targets through FPGA to HardWire conversions since 1991. With over 500 device conversions completed, the Xilinx HardWire conversion methodology is finely tuned to support all Xilinx features and functionality. All of the advanced Xilinx features such as Select-RAM, JTAG, and LogiCore functions are fully supported by the HardWire methodology. No one in the industry has more experience converting Xilinx designs than Xilinx. Because of our innovative migration methodology, first-time success rates are greater than 95%.

Unique HardWire Gate Array Benefits

There are many benefits to using the Xilinx FPGA/HardWire Gate Array combination:

  • Reduces system/device development time
  • Allows concurrent software development and debug
  • Production begins with FPGAs. Commit to mask programmed device only when ready
  • No test vectors to write
  • Same packaging and pinouts
  • No additional engineering effort to achieve the cost reduction
  • Peace-of-Mind Guarantee

    The HardWire Gate Array Guarantee

    Xilinx offers the Peace-of-Mind guarantee with each HardWire migration. Should an error occur during the conversion process, whether it is the customer's error or a Xilinx error, Xilinx will discount FPGA devices for up to 12 weeks. Only Xilinx can offer this guaranteed risk-free conversion process.

    HardWire Gate Array Diagram

    The HardWire Gate Array is completely interchangeable with its FPGA counterpart. No PCB change is required. HardWire device phase-in is seamless and FPGAs can always be substituted for quick production boosts or for inventory management at equipment end-of-life.

    HardWire Design Once Methodology Diagram

    Migration from the FPGA to a HardWire Gate Array is simple. Xilinx implements the design at the physical database level from the completed FPGA design file. No recapture in third-party cell libraries, redesign of logic, extensive resimulation or test vector generation is required. By using proprietary Automatic Test Pattern Generation (ATPG) and patented test logic, Xilinx achieves better than 95% fault coverage on every design.

    Complete HardWire Product Families

    For every Xilinx FPGA and for the XC9500 family of CPLDs, there is a corresponding HardWire Gate Array. HardWire is available in commercial and industrial grade temperature ranges. Mimimum order requirements are extremely reasonable, with some products as low as 1500 pieces per year. All HardWire device package specifications exactly match the FPGA or CPLD package specifications.

    		HardWire Family Product Chart
    CPLD/FPGA HardWire Device
    XC4000E
    XC4000EX
    XC5200
    XC9500*    		 XC4400E
    XH4000EX
    XC5400
    XH9500
    * 108 Macrocells and up

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