#!/bin/csh -f

set version = "1.15"
set debug = FALSE
set validcomps = "ACCUM ADD_SUB CLK_DIV COMPARE COUNTER DATA_REG DECODE INC_DEC SHIFT"
set sup_families = "XC4000 XC5200"
set tdis_devices = "4002 4003 4004 4005 4006 4008 4010 4013 4025 5202 5204 5206 5210 5215"
set sup_devices = "4002APQ100 4003PQ100 4004APQ160 4005PQ208 4006PQ208 4008PQ208 4010PQ208 4013PQ240 4025PG299 5202PG156 5204PQ160 5206PG191 5210PG223 5215PG299"
set sup_packages = "4002p100.pkg 4003p100.pkg 4004p160.pkg 4005p208.pkg 4006p208.pkg 4008p208.pkg 4010p208.pkg 4013p240.pkg 4025g299.pkg 5202g156.pkg 5204p160.pkg 5206g191.pkg 5210g223.pkg 5215g299.pkg"

##################
# Display header #
##################

rm -f xbloxgen.log
touch xbloxgen.log
#
echo ""
echo "XBLOXGEN Version ${version}"
echo "XBLOXGEN Version ${version}" >> xbloxgen.log
echo "" >> xbloxgen.log
#
set vhdl = undefined
set verilog = undefined
set comptype = undefined
#
if ( ${#argv} > 0 ) then
  goto parse_params
endif

###################
# Look for X-BLOX #
###################

lookforblox:
#
rm -f xblox.help
echo ""
echo -n "Looking for XBLOX..."
(xblox > xblox.help) >& /dev/null
if (`wc -l xblox.help | awk '{if (NR = 1) {print $1}}'` == 0) then
  rm -f xblox.help
  echo "XBLOX NOT found."
  echo ""
  echo "    Error:  Could not find the executible 'xblox'."
  echo "            Please set up the DS380 and re-run xbloxgen."
  echo ""
  echo "" >> xbloxgen.log
  echo "    Error:  Could not find the executible 'xblox'." >> xbloxgen.log
  echo "            Please set up the DS380 and re-run xbloxgen." >> xbloxgen.log
  echo "" >> xbloxgen.log
  goto displayhelp
endif
echo "XBLOX found."
echo "XBLOX found." >> xbloxgen.log
rm -f xblox.help
goto lookfordatafiles

#######################
# Look for data files #
#######################

lookfordatafiles:
#
echo ""
echo "Looking for data files:"
echo "" >> xbloxgen.log
echo "Looking for data files:" >> xbloxgen.log
goto lookforpartlist

#########################
# Look for PARTLIST.XCT #
#########################

lookforpartlist:
#
echo -n "    partlist.xct "
if ( -e partlist.xct ) then
  echo "found."
  echo "    partlist.xct found." >> xbloxgen.log
  goto lookforsupported
else
  if ( -e ~/partlist.xct ) then
    echo "found."
    echo "    partlist.xct found." >> xbloxgen.log
    goto lookforsupported
  else
    if (${?XACT}) then
      set tempxact = `echo $XACT | sed s/:/" "/g`
      set found = 0
      foreach g (${tempxact})
        if ((-e ${g}/data/partlist.xct) && (${found} == "0")) then
          echo "found."
          echo "    partlist.xct found." >> xbloxgen.log
          set found = 1
          set foundone = 1
        endif
      end
      if (${found} != "1") then
        echo "NOT found."
        echo ""
        echo "    Error:  Could not find the file 'partlist.xct'."
        echo "            Please set up the DS502 and re-run xbloxgen."
        echo ""
        echo "" >> xbloxgen.log
        echo "    Error:  Could not find the file 'partlist.xct'." >> xbloxgen.log
        echo "            Please set up the DS502 and re-run xbloxgen." >> xbloxgen.log
        echo "" >> xbloxgen.log
        goto displayhelp  
      endif
    else
      echo "NOT found."
      echo ""
        echo "    Error:  Could not find the file 'partlist.xct'."
        echo "            Please set up the DS502 and re-run xbloxgen."
        echo ""
        echo "" >> xbloxgen.log
        echo "    Error:  Could not find the file 'partlist.xct'." >> xbloxgen.log
        echo "            Please set up the DS502 and re-run xbloxgen." >> xbloxgen.log
        echo "" >> xbloxgen.log
        goto displayhelp  
    endif
  endif
endif
goto lookforsupported

###############################
# Look for supported packages #
###############################

lookforsupported:
#
set foundone = 0
set counti = 0
set found_devices = ""
set dis_devices = ""
  foreach f (${sup_packages})
    @ counti = $counti + 1
    echo -n "    $f "
    if ( -e $f ) then
      echo "found."
      echo "    ${f} found." >> xbloxgen.log
      set foundone = 1
      set tempi = 1
      foreach h (${sup_devices})
        if (${tempi} == ${counti}) then
          set found_devices = `echo "${found_devices} ${h}"`
        endif
        @ tempi = $tempi + 1
      end
      set tempi = 1
      foreach h (${tdis_devices})
        if (${tempi} == ${counti}) then
          set dis_devices = `echo "${dis_devices} ${h}"`
        endif
        @ tempi = $tempi + 1
      end
    else
      if ( -e ~/${f} ) then
        echo "found."
        echo "    ${f} found." >> xbloxgen.log
        set foundone = 1
        set tempi = 1
        foreach h (${sup_devices})
          if (${tempi} == ${counti}) then
            set found_devices = `echo "${found_devices} ${h}"`
          endif
          @ tempi = $tempi + 1
        end
        set tempi = 1
        foreach h (${tdis_devices})
          if (${tempi} == ${counti}) then
            set dis_devices = `echo "${dis_devices} ${h}"`
          endif
          @ tempi = $tempi + 1
        end
      else
        if (${?XACT}) then
          set tempxact = `echo $XACT | sed s/:/" "/g`
          set found = 0
          foreach g (${tempxact})
            if ((-e ${g}/data/$f) && (${found} == "0")) then
              echo "found."
              echo "    ${f} found." >> xbloxgen.log
              set found = 1
              set foundone = 1
              set tempi = 1
              foreach h (${sup_devices})
                if (${tempi} == ${counti}) then
                  set found_devices = `echo "${found_devices} ${h}"`
                endif
                @ tempi = $tempi + 1
              end
              set tempi = 1
              foreach h (${tdis_devices})
                if (${tempi} == ${counti}) then
                  set dis_devices = `echo "${dis_devices} ${h}"`
                endif
                @ tempi = $tempi + 1
              end
          endif
          end
          if (${found} != "1") then
            echo "NOT found."
            echo "    ${f} NOT found." >> xbloxgen.log
          endif
        endif
      endif
    endif
  end
if (${foundone} != "1") then
  echo ""
  echo "    Error:  Could not find any of the supported package files."
  echo "            Please set up the DS502 and re-run xbloxgen."
  echo ""
  echo "" >> xbloxgen.log
  echo "    Error:  Could not find any of the supported package files." >> xbloxgen.log
  echo "            Please set up the DS502 and re-run xbloxgen." >> xbloxgen.log
  echo "" >> xbloxgen.log
  goto displayhelp  
endif
echo "" >> xbloxgen.log
goto getcomptype

######################
# Get component type #
######################

getcomptype:
#
if (${comptype} == undefined) then
  echo ""
  echo "  The following types of X-BLOX components"
  echo "  can be generated using xbloxgen:"
  echo ""
  echo "          1)  ACCUM    => Accumulator"
  echo "          2)  ADD_SUB  => Adder/Subtractor"
  echo "          3)  CLK_DIV  => Clock Divider"
  echo "          4)  COMPARE  => Comparators"
  echo "          5)  COUNTER  => Universal Counter"
  echo "          6)  DATA_REG => Data Register"
  echo "          7)  DECODE   => Decoder/Demux"
  echo "          8)  INC_DEC  => Incrementor/Decrementor"
  echo "          9)  SHIFT    => Universal Shift Register"
  echo ""
  echo "  Select the type of component to be generated"
  echo -n "  by entering its number (enter 'q' to quit):  "
  set comptype = $<
endif
############################
# Determine component type #
############################

determinetype:
#  
switch (${comptype})
  case 1:
    set comptype = ACCUM
    breaksw 
  case 2:
    set comptype = ADD_SUB
    breaksw
  case 3:
    set comptype = CLK_DIV
    breaksw
  case 4:
    set comptype = COMPARE
    breaksw
  case 5:
    set comptype = COUNTER
    breaksw
  case 6:
    set comptype = DATA_REG
    breaksw
  case 7:
    set comptype = DECODE
    breaksw
  case 8:
    set comptype = INC_DEC
    breaksw
  case 9:
    set comptype = SHIFT
    breaksw
  case q:
    goto end
    breaksw 
  case Q:
    goto end
    breaksw 
  default:
    echo ""
    echo "    Error:  The entry '${comptype}' is invalid."
    echo "            The valid entries are 1 through 9."
    set comptype = undefined
    goto getcomptype
    breaksw
endsw
#
echo ""
echo "The following questions will define the characteristics"
echo "of the ${comptype} to be generated."
echo ""
goto initchars

#######################################################
# ***** Create Components - Set Characteristics ***** #
#######################################################

################
# Create ACCUM #
################

setchar_ACCUM:
#
set busdefpin = "B"
set p_b = yes
set p_clk = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_aencoding
  endif
endif
if (${p_addsub} == undefined) then
  goto define_addsubp    
endif
if (${p_c_in} == undefined) then
  set pintoget = "c_in"
  set direction = "input"
  goto define_genericp    
endif
if (${p_load} == undefined) then
  goto define_loadp
endif
if (${p_clk_en} == undefined) then
  set pintoget = "clk_en"
  set direction = "input"
  goto define_genericp
endif
if (${asyncp} == undefined) then
  goto define_asyncp
endif
if (${syncp} == undefined) then
  goto define_syncp
endif
if (${p_q_out} == undefined) then
  set pintoget = "q_out"
  set direction = "parallel output"
  goto define_genericp
endif
if (${p_c_out} == undefined) then
  set pintoget = "c_out"
  set direction = "output"
  goto define_genericp
endif
if (${p_ovfl} == undefined) then
  set pintoget = "ovfl"
  set direction = "output"
  goto define_genericp
endif
if (${a_aristyle} == undefined) then
  goto define_aristylea
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
#
goto generate

##################
# Create ADD_SUB #
##################

setchar_ADD_SUB:
#
set busdefpin = "B"
set p_a = yes
set p_b = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_aencoding
  endif
endif
if (${p_addsub} == undefined) then
  goto define_addsubp    
endif
if (${p_c_in} == undefined) then
  set pintoget = "c_in"
  set direction = "input"
  goto define_genericp    
endif
if (${p_func} == undefined) then
  set pintoget = "func"
  set direction = "parallel output"
  goto define_genericp
endif
if (${p_ovfl} == undefined) then
  set pintoget = "ovfl"
  set direction = "output"
  goto define_genericp
endif
if (${p_c_out} == undefined) then
  set pintoget = "c_out"
  set direction = "output"
  goto define_genericp
endif
if (${a_aristyle} == undefined) then
  goto define_aristylea
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
#
goto generate

##################
# Create CLK_DIV #
##################

setchar_CLK_DIV:
#
set busdefpin = "NONE"
set p_clk = yes
set p_clk_out = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
set a_asyncval = 0
if (${asyncp} == undefined) then
  goto define_asyncp
endif
set a_asyncval = undefined
set a_syncval = 0
if (${syncp} == undefined) then
  goto define_syncp
endif
set a_syncval = undefined
if (${p_en} == undefined) then
  set pintoget = "en"
  set direction = "input"
  goto define_genericp
endif
if (${a_divide_by} == undefined) then
  goto define_divide_bya
endif
if ("${a_duty_cycle}" == undefined) then
  goto define_duty_cyclea
endif
goto generate

##################
# Create COMPARE #
##################

setchar_COMPARE:
#
set busdefpin = "A"
set p_a = yes
set p_b = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_sencoding
  endif
endif
if (${p_a_eq_b} == undefined) then
  set pintoget = "a_eq_b"
  set direction = "output"
  goto define_genericp
endif
if (${p_a_ne_b} == undefined) then
  set pintoget = "a_ne_b"
  set direction = "output"
  goto define_genericp
endif
if (${p_a_lt_b} == undefined) then
  set pintoget = "a_lt_b"
  set direction = "output"
  goto define_genericp
endif
if (${p_a_gt_b} == undefined) then
  set pintoget = "a_gt_b"
  set direction = "output"
  goto define_genericp
endif
if (${p_a_le_b} == undefined) then
  set pintoget = "a_le_b"
  set direction = "output"
  goto define_genericp
endif
if (${p_a_ge_b} == undefined) then
  set pintoget = "a_ge_b"
  set direction = "output"
  goto define_genericp
endif
if (${a_comstyle} == undefined) then
  goto define_comstylea
endif
#
goto generate

##################
# Create COUNTER #
##################

setchar_COUNTER:
#
set busdefpin = "COMPONENT"
set p_clk = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_aencoding
  endif
endif
if (${p_load} == undefined) then
  goto define_loadp
endif
if (${p_load} == "yes") then
  set p_d_in = yes
else
  set p_d_in = no
endif
if (${p_up_dn} == undefined) then
  goto define_up_dnp
endif
if (${asyncp} == undefined) then
  goto define_asyncp
endif
if (${syncp} == undefined) then
  goto define_syncp
endif
if (${p_clk_en} == undefined) then
  set pintoget = "clk_en"
  set direction = "input"
  goto define_genericp
endif
if (${p_q_out} == undefined) then
  set pintoget = "q_out"
  set direction = "parallel output"
  goto define_genericp
endif
if (${p_term_cnt} == undefined) then
  set pintoget = "term_cnt"
  set direction = "output"
  goto define_genericp
endif
if (${a_coustyle} == undefined) then
  goto define_coustylea
endif
if ((${a_countto} == undefined) && (${a_coustyle} != "ONE_HOT")) then
  goto define_counttoa
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
#
goto generate


###################
# Create DATA_REG #
###################

setchar_DATA_REG:
#
set busdefpin = "COMPONENT"
set p_d_in = "yes"
set p_clk = "yes"
set p_q_out = "yes"
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_sencoding
  endif
endif
if (${a_asyncval} == undefined) then
  echo "  To determine the initial startup values of the"
  echo "  flip-flops, the asynchronous value must be defined."
  echo ""
  goto define_asyncvala
endif
if (${asyncp} == undefined) then
  goto define_asyncp
endif
if (${syncp} == undefined) then
  goto define_syncp
endif
if (${p_clk_en} == undefined) then
  set pintoget = "clk_en"
  set direction = "input"
  goto define_genericp
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
goto generate

#################
# Create DECODE #
#################

setchar_DECODE:
#
set busdefpin = "DECODE"
set p_sel = yes
set p_d_out = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${sel_size} == undefined) then
  goto define_sel_size
endif
if (${selencoding} == undefined) then
  if (${sel_size} == "0") then
    set selencoding = BIT
  else
    goto define_selencoding
  endif
endif
if (${d_out_size} == undefined) then
  goto define_d_out_size
endif
if (${p_en} == undefined) then
  set pintoget = "en"
  set direction = "input"
  goto define_genericp
endif
if (${p_sel_error} == undefined) then
  set pintoget = "sel_error"
  set direction = "output"
  goto define_genericp
endif
goto generate

##################
# Create INC_DEC #
##################

setchar_INC_DEC:
#
set busdefpin = "A"
set p_a = yes
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_aencoding
  endif
endif
if (${p_inc_dec} == undefined) then
  goto define_inc_decp
endif
if (${a_inc_by} == undefined) then
  goto define_inc_bya
endif
if (${p_func} == undefined) then
  set pintoget = "func"
  set direction = "parallel output"
  goto define_genericp
endif
if (${p_ovfl} == undefined) then
  set pintoget = "ovfl"
  set direction = "output"
  goto define_genericp
endif
if (${p_c_out} == undefined) then
  set pintoget = "c_out"
  set direction = "output"
  goto define_genericp
endif
if (${a_aristyle} == undefined) then
  goto define_aristylea
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
goto generate

################
# Create SHIFT #
################

setchar_SHIFT:
#
set busdefpin = "COMPONENT"
set p_clk = "yes"
#
if (${libname} == undefined) then
  goto define_libname
endif
if (${size} == undefined) then
  goto define_size
endif
if (${encoding} == undefined) then
  if (${size} == "0") then
    set encoding = BIT
  else
    goto define_sencoding
  endif
endif
if (${a_asyncval} == undefined) then
  echo "  To determine the initial startup values of the"
  echo "  flip-flops, the asynchronous value must be defined."
  echo ""
  goto define_asyncvala
endif
if (${asyncp} == undefined) then
  goto define_asyncp
endif
if (${syncp} == undefined) then
  goto define_syncp
endif
if (${p_load} == undefined) then
  goto define_loadp
endif
if (${p_load} == "yes") then
  set p_par_in = yes
else
  set p_par_in = no
endif
if (${p_ls_in} == undefined) then
  set pintoget = "ls_in"
  set direction = "input (used while shifting left)"
  goto define_genericp
endif
if (${p_ms_in} == undefined) then
  set pintoget = "ms_in"
  set direction = "input (used while shifting right)"
  goto define_genericp
endif
if (${p_right_left} == undefined) then
  goto define_right_leftp
endif
if (${p_clk_en} == undefined) then
  set pintoget = "clk_en"
  set direction = "input"
  goto define_genericp
endif
if (${p_par_out} == undefined) then
  set pintoget = "par_out"
  set direction = "parallel output"
  goto define_genericp
endif
if (${p_ls_out} == undefined) then
  set pintoget = "ls_out"
  set direction = "output (used while shifting right)"
  goto define_genericp
endif
if (${p_ms_out} == undefined) then
  set pintoget = "ms_out"
  set direction = "output (used while shifting left)"
  goto define_genericp
endif
if (${a_sftstyle} == undefined) then
  goto define_sftstylea
endif
if (${a_rloc} == undefined) then
  goto define_rloca
endif
goto generate

##############################################
# ***** Generate the desired component ***** #
##############################################

generate:
#
set lclibname = `echo ${libname} | tr '[A-Z]' '[a-z]'`
set libname = ${lclibname}
rm -f ${libname}.xtg
rm -f miscrecs.tmp
rm -f siglist.tmp
rm -f vhdldef.sigs
rm -f vhdlins.sigs
rm -f verdef.sigs
rm -f verins.sigs
touch miscrecs.tmp
touch vhdldef.sigs
touch vhdlins.sigs
touch verdef.sigs
touch verins.sigs
#
goto getparttype
#
generate_partreturn:
#
echo "Generating ${comptype} with the following characteristics:"
echo ""
echo "Generating ${comptype} with the following characteristics:" >> xbloxgen.log
echo "" >> xbloxgen.log
echo "LCANET, 5" > ${libname}.xtg
echo "PROG, XBLOXGEN, ${version}" >> ${libname}.xtg
echo "PROG, XNFMERGE, 5.1.0" >> ${libname}.xtg
echo "PROG, XNFPREP, 5.1.0" >> ${libname}.xtg
if (${?chosenpkg}) then
  echo "PART, ${chosenpkg}" >> ${libname}.xtg
  echo "  smallest device:  ${chosen}"
  echo "  smallest device:  ${chosen}" >> xbloxgen.log
else
  echo "PART, 4013MQ240" >> ${libname}.xtg
  echo "  smallest device:  4013"
  echo "  smallest device:  4013" >> xbloxgen.log
endif
#
if (${size} != undefined) then
  @ displaysize = ${size} + 1
  echo "             size:  ${displaysize}-bit"
  echo "             size:  ${displaysize}-bit" >> xbloxgen.log
endif
if (${sel_size} != undefined) then
  @ displaysize = ${sel_size} + 1
  echo "      select size:  ${displaysize}-bit"
  echo "      select size:  ${displaysize}-bit" >> xbloxgen.log
endif
if (${d_out_size} != undefined) then
  @ displaysize = ${d_out_size} + 1
  echo "       d_out size:  ${displaysize}-bit"
  echo "       d_out size:  ${displaysize}-bit" >> xbloxgen.log
endif
if (${encoding} != undefined) then
  echo "         encoding:  ${encoding}"
  echo "         encoding:  ${encoding}" >> xbloxgen.log
endif
if (${selencoding} != undefined) then
  echo "  select encoding:  ${selencoding}"
  echo "  select encoding:  ${selencoding}" >> xbloxgen.log
endif
#
#########################################
# Write X-BLOX bus_def to component.xtg #
#########################################
#
if ((${busdefpin} != "COMPONENT") && (${busdefpin} != "NONE")) then
  if (${busdefpin} != "DECODE") then
    echo "SYM, BUS_DEF, BUS_DEF, DEF=BLOX, LIBVER=2.0.0, =BOUNDS=${size}:0, =ENCODING=${encoding}" >> ${libname}.xtg
    echo "PIN, XBLOX_BUS, I, ${busdefpin}" >> ${libname}.xtg
    echo "END" >> ${libname}.xtg
  else
    echo "SYM, BUS_DEF1, BUS_DEF, DEF=BLOX, LIBVER=2.0.0, =BOUNDS=${sel_size}:0, =ENCODING=${selencoding}" >> ${libname}.xtg
    echo "PIN, XBLOX_BUS, I, SEL" >> ${libname}.xtg
    echo "END" >> ${libname}.xtg    
    echo "SYM, BUS_DEF2, BUS_DEF, DEF=BLOX, LIBVER=2.0.0, =BOUNDS=${d_out_size}:0, =ENCODING=ONE_HOT" >> ${libname}.xtg
    echo "PIN, XBLOX_BUS, I, D_OUT" >> ${libname}.xtg
    echo "END" >> ${libname}.xtg    
  endif
endif
#
###################################
# Build X-BLOX component sym line #
###################################
#
set symline = "SYM, GENCOMP, ${comptype}, DEF=BLOX, LIBVER=2.0.0"
#
if (${busdefpin} == "COMPONENT") then
   set symline = `echo "${symline}, =BOUNDS=${size}:0, =ENCODING=${encoding}"`
endif
if (${a_aristyle} != undefined) then
  echo "            style:  ${a_aristyle}"
  echo "            style:  ${a_aristyle}" >> xbloxgen.log
  set symline = `echo "${symline}, =STYLE=${a_aristyle}"`
endif
if ((${a_comstyle} != undefined) && (${a_comstyle} != "XBLOX")) then
  echo "            style:  ${a_comstyle}"
  echo "            style:  ${a_comstyle}" >> xbloxgen.log
  set symline = `echo "${symline}, =STYLE=${a_comstyle}"`
endif
if ((${a_coustyle} != undefined) && (${a_coustyle} != "XBLOX")) then
  echo "            style:  ${a_coustyle}"
  echo "            style:  ${a_coustyle}" >> xbloxgen.log
  set symline = `echo "${symline}, =STYLE=${a_coustyle}"`
endif
if (${a_sftstyle} != undefined) then
  echo "            style:  ${a_sftstyle}"
  echo "            style:  ${a_sftstyle}" >> xbloxgen.log
  set symline = `echo "${symline}, =STYLE=${a_sftstyle}"`
endif
if (${a_countto} != undefined) then
  echo "         count to:  ${a_countto}"
  echo "         count to:  ${a_countto}" >> xbloxgen.log
  if (${a_countto} != "max") then
    set symline = `echo "${symline}, =COUNT_TO=${a_countto}"`
  endif
endif
if (${a_inc_by} != undefined) then
  echo "      inc/dec val:  ${a_inc_by}"
  echo "      inc/dec val:  ${a_inc_by}" >> xbloxgen.log
  if (${a_inc_by} != "1") then
    set symline = `echo "${symline}, =INC_BY=${a_inc_by}"`
  endif
endif
if (${a_rloc} != undefined) then
  echo "       create rpm:  ${a_rloc}"
  echo "       create rpm:  ${a_rloc}" >> xbloxgen.log
  set symline = `echo "${symline}, =USE_RLOC=${a_rloc}"`
endif
if (${a_divide_by} != undefined) then
  echo "        divide_by:  ${a_divide_by}"
  echo "        divide_by:  ${a_divide_by}" >> xbloxgen.log
  set symline = `echo "${symline}, =DIVIDE_BY=${a_divide_by}"`
endif
if ("${a_duty_cycle}" != undefined) then
  echo "      clocks high:  ${a_duty_cycle}"
  echo "      clocks high:  ${a_duty_cycle}" >> xbloxgen.log
  if ("${a_duty_cycle}" != "HALF DIVIDE_BY") then
    set symline = `echo "${symline}, =DUTY_CYCLE=${a_duty_cycle}"`
  endif
endif
if (${a_asyncval} != undefined) then
  echo "        async_val:  ${a_asyncval}"
  echo "        async_val:  ${a_asyncval}" >> xbloxgen.log
  set symline = `echo "${symline}, =ASYNC_VAL=${a_asyncval}"`
endif
if (${a_syncval} != undefined) then
  echo "         sync_val:  ${a_syncval}"
  echo "         sync_val:  ${a_syncval}" >> xbloxgen.log
  set symline = `echo "${symline}, =SYNC_VAL=${a_syncval}"`
endif
#
####################################################
# Write X-BLOX component sym line to component.xtg #
####################################################
#
echo ${symline} >> ${libname}.xtg
#
######################################################
# Write X-BLOX component input pins to component.xtg #
######################################################
#
if (${asyncp} != undefined) then
  echo "       async_ctrl:  ${asyncp}"
  echo "       async_ctrl:  ${asyncp}" >> xbloxgen.log
  if (${asyncp} == "yes") then
    echo "PIN, ASYNC_CTRL, I, ASYNC_CTRL" >> ${libname}.xtg
    echo "            ASYNC_CTRL:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            ASYNC_CTRL=>ASYNC_CTRL_SIG," >> vhdlins.sigs
    echo "input ASYNC_CTRL_SIG;" >> verdef.sigs
    echo "            .ASYNC_CTRL(ASYNC_CTRL_SIG)," >> verins.sigs
  endif
endif
if (${syncp} != undefined) then
  echo "        sync_ctrl:  ${syncp}"
  echo "        sync_ctrl:  ${syncp}" >> xbloxgen.log
  if (${syncp} == "yes") then
    echo "PIN, SYNC_CTRL, I, SYNC_CTRL" >> ${libname}.xtg
    echo "            SYNC_CTRL:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            SYNC_CTRL=>SYNC_CTRL_SIG," >> vhdlins.sigs
    echo "input SYNC_CTRL_SIG;" >> verdef.sigs
    echo "            .SYNC_CTRL(SYNC_CTRL_SIG)," >> verins.sigs
  endif
endif
if (${p_addsub} != undefined) then
  echo "        operation:  ${p_addsub}"
  echo "        operation:  ${p_addsub}" >> xbloxgen.log
  switch (${p_addsub})
    case ADD:
      echo "PIN, ADD_SUB, I, ADD" >> ${libname}.xtg
      echo "PWR, 1, ADD" >> miscrecs.tmp
      breaksw
    case SUB:
      echo "PIN, ADD_SUB, I, SUB" >> ${libname}.xtg
      echo "PWR, 0, SUB" >> miscrecs.tmp
      breaksw
    case ADD_SUB:
      echo "PIN, ADD_SUB, I, ADD_SUB" >> ${libname}.xtg
      echo "            ADD_SUB:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            ADD_SUB=>ADD_SUB_SIG," >> vhdlins.sigs
      echo "input ADD_SUB_SIG;" >> verdef.sigs
      echo "            .ADD_SUB(ADD_SUB_SIG)," >> verins.sigs
      breaksw
  endsw
endif
if (${p_up_dn} != undefined) then
  echo "        direction:  ${p_up_dn}"
  echo "        direction:  ${p_up_dn}" >> xbloxgen.log
  switch (${p_up_dn})
    case UP:
      echo "PIN, UP_DN, I, UP" >> ${libname}.xtg
      echo "PWR, 1, UP" >> miscrecs.tmp
      breaksw
    case DOWN:
      echo "PIN, UP_DN, I, DOWN" >> ${libname}.xtg
      echo "PWR, 0, DOWN" >> miscrecs.tmp
      breaksw
    case UP/DOWN:
      echo "PIN, UP_DN, I, UP_DOWN" >> ${libname}.xtg
      echo "            UP_DOWN:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            UP_DOWN=>UP_DOWN_SIG," >> vhdlins.sigs
      echo "input UP_DOWN_SIG;" >> verdef.sigs
      echo "            .UP_DOWN(UP_DOWN_SIG)," >> verins.sigs
      breaksw
  endsw
endif
if (${p_inc_dec} != undefined) then
  echo "        operation:  ${p_inc_dec}"
  echo "        operation:  ${p_inc_dec}" >> xbloxgen.log
  switch (${p_inc_dec})
    case INC:
      echo "PIN, INC_DEC, I, INC" >> ${libname}.xtg
      echo "PWR, 1, INC" >> miscrecs.tmp
      breaksw
    case DEC:
      echo "PIN, INC_DEC, I, DEC" >> ${libname}.xtg
      echo "PWR, 0, DEC" >> miscrecs.tmp
      breaksw
    case INC/DEC:
      echo "PIN, INC_DEC, I, INC_DEC" >> ${libname}.xtg
      echo "            INC_DEC:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            INC_DEC=>INC_DEC_SIG," >> vhdlins.sigs
      echo "input INC_DEC_SIG;" >> verdef.sigs
      echo "            .INC_DEC(INC_DEC_SIG)," >> verins.sigs
      breaksw
  endsw
endif
if (${p_right_left} != undefined) then
  echo "        operation:  ${p_right_left}"
  echo "        operation:  ${p_right_left}" >> xbloxgen.log
  switch (${p_right_left})
    case RIGHT:
      echo "PIN, RIGHT_LEFT, I, RIGHT" >> ${libname}.xtg
      echo "PWR, 1, RIGHT" >> miscrecs.tmp
      breaksw
    case LEFT:
      echo "PIN, RIGHT_LEFT, I, LEFT" >> ${libname}.xtg
      echo "PWR, 0, LEFT" >> miscrecs.tmp
      breaksw
    case RIGHT/LEFT:
      echo "PIN, RIGHT_LEFT, I, RIGHT_LEFT" >> ${libname}.xtg
      echo "            RIGHT_LEFT:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            RIGHT_LEFT=>RIGHT_LEFT_SIG," >> vhdlins.sigs
      echo "input RIGHT_LEFT_SIG;" >> verdef.sigs
      echo "            .RIGHT_LEFT(RIGHT_LEFT_SIG)," >> verins.sigs
      breaksw
  endsw
endif
if (${p_a} != undefined) then
  echo "     a input used:  ${p_a}"
  echo "     a input used:  ${p_a}" >> xbloxgen.log
  if (${p_a} == "yes") then
    echo "PIN, A, I, A" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            A:  in  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            A=>A_BUS," >> vhdlins.sigs
      echo "input [${size}:0] A_BUS;" >> verdef.sigs
      echo "            .A(A_BUS)," >> verins.sigs
    else
      echo "            A:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            A=>A_SIG," >> vhdlins.sigs
      echo "input A_SIG;" >> verdef.sigs
      echo "            .A(A_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_b} != undefined) then
  echo "     b input used:  ${p_b}"
  echo "     b input used:  ${p_b}" >> xbloxgen.log
  if (${p_b} == "yes") then
    echo "PIN, B, I, B" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            B:  in  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            B=>B_BUS," >> vhdlins.sigs
      echo "input [${size}:0] B_BUS;" >> verdef.sigs
      echo "            .B(B_BUS)," >> verins.sigs
    else
      echo "            B:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            B=>B_SIG," >> vhdlins.sigs
      echo "input B_SIG;" >> verdef.sigs
      echo "            .B(B_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_d_in} != undefined) then
  echo "             d_in:  ${p_d_in}"
  echo "             d_in:  ${p_d_in}" >> xbloxgen.log
  if (${p_d_in} == "yes") then
    echo "PIN, D_IN, I, D_IN" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            D_IN:  in  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            D_IN=>D_IN_BUS," >> vhdlins.sigs
      echo "input [${size}:0] D_IN_BUS;" >> verdef.sigs
      echo "            .D_IN(D_IN_BUS)," >> verins.sigs
    else
      echo "            D_IN:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            D_IN=>D_IN_SIG," >> vhdlins.sigs
      echo "input D_IN_SIG;" >> verdef.sigs
      echo "            .D_IN(D_IN_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_par_in} != undefined) then
  echo "           par_in:  ${p_par_in}"
  echo "           par_in:  ${p_par_in}" >> xbloxgen.log
  if (${p_par_in} == "yes") then
    echo "PIN, PAR_IN, I, PAR_IN" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            PAR_IN:  in  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            PAR_IN=>PAR_IN_BUS," >> vhdlins.sigs
      echo "input [${size}:0] PAR_IN_BUS;" >> verdef.sigs
      echo "            .PAR_IN(PAR_IN_BUS)," >> verins.sigs
    else
      echo "            PAR_IN:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            PAR_IN=>PAR_IN_SIG," >> vhdlins.sigs
      echo "input PAR_IN_SIG;" >> verdef.sigs
      echo "            .PAR_IN(PAR_IN_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_sel} != undefined) then
  echo "           select:  ${p_sel}"
  echo "           select:  ${p_sel}" >> xbloxgen.log
  if (${p_sel} == "yes") then
    echo "PIN, SEL, I, SEL" >> ${libname}.xtg
    if (${sel_size} != "0") then
      echo "            SEL:  in  STD_LOGIC_VECTOR (${sel_size} downto 0);" >> vhdldef.sigs
      echo "            SEL=>SEL_BUS," >> vhdlins.sigs
      echo "input [${sel_size}:0] SEL_BUS;" >> verdef.sigs
      echo "            .SEL(SEL_BUS)," >> verins.sigs
    else
      echo "            SEL:  in  STD_LOGIC;" >> vhdldef.sigs
      echo "            SEL=>SEL_SIG," >> vhdlins.sigs
      echo "input SEL_SIG;" >> verdef.sigs
      echo "            .SEL(SEL_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_clk} != undefined) then
  echo "              clk:  ${p_clk}"
  echo "              clk:  ${p_clk}" >> xbloxgen.log
  if (${p_clk} == "yes") then
    echo "PIN, CLOCK, I, CLOCK" >> ${libname}.xtg
    echo "            CLOCK:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            CLOCK=>CLOCK_SIG," >> vhdlins.sigs
    echo "input CLOCK_SIG;" >> verdef.sigs
    echo "            .CLOCK(CLOCK_SIG)," >> verins.sigs
  endif
endif
if (${p_c_in} != undefined) then
  echo "         carry-in:  ${p_c_in}"
  echo "         carry-in:  ${p_c_in}" >> xbloxgen.log
  if (${p_c_in} == "yes") then
    echo "PIN, C_IN, I, C_IN" >> ${libname}.xtg
    echo "            C_IN:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            C_IN=>C_IN_SIG," >> vhdlins.sigs
    echo "input C_IN_SIG;" >> verdef.sigs
    echo "            .C_IN(C_IN_SIG)," >> verins.sigs
  endif
endif
if (${p_load} != undefined) then
  echo "             load:  ${p_load}"
  echo "             load:  ${p_load}" >> xbloxgen.log
  if (${p_load} == "yes") then
    echo "PIN, LOAD, I, LOAD" >> ${libname}.xtg
    echo "            LOAD:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            LOAD=>LOAD_SIG," >> vhdlins.sigs
    echo "input LOAD_SIG;" >> verdef.sigs
    echo "            .LOAD(LOAD_SIG)," >> verins.sigs
  endif
endif
if (${p_ms_in} != undefined) then
  echo "            ms_in:  ${p_ms_in}"
  echo "            ms_in:  ${p_ms_in}" >> xbloxgen.log
  if (${p_ms_in} == "yes") then
    echo "PIN, MS_IN, I, MS_IN" >> ${libname}.xtg
    echo "            MS_IN:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            MS_IN=>MS_IN_SIG," >> vhdlins.sigs
    echo "input MS_IN_SIG;" >> verdef.sigs
    echo "            .MS_IN(MS_IN_SIG)," >> verins.sigs
  endif
endif
if (${p_ls_in} != undefined) then
  echo "            ls_in:  ${p_ls_in}"
  echo "            ls_in:  ${p_ls_in}" >> xbloxgen.log
  if (${p_ls_in} == "yes") then
    echo "PIN, LS_IN, I, LS_IN" >> ${libname}.xtg
    echo "            LS_IN:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            LS_IN=>LS_IN_SIG," >> vhdlins.sigs
    echo "input LS_IN_SIG;" >> verdef.sigs
    echo "            .LS_IN(LS_IN_SIG)," >> verins.sigs
  endif
endif
if (${p_clk_en} != undefined) then
  echo "          clk_ena:  ${p_clk_en}"
  echo "          clk_ena:  ${p_clk_en}" >> xbloxgen.log
  if (${p_clk_en} == "yes") then
    echo "PIN, CLK_EN, I, CLK_EN" >> ${libname}.xtg
    echo "            CLK_EN:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            CLK_EN=>CLK_EN_SIG," >> vhdlins.sigs
    echo "input CLK_EN_SIG;" >> verdef.sigs
    echo "            .CLK_EN(CLK_EN_SIG)," >> verins.sigs
  endif
endif
if (${p_en} != undefined) then
  echo "               en:  ${p_en}"
  echo "               en:  ${p_en}" >> xbloxgen.log
  if (${p_en} == "yes") then
    echo "PIN, EN, I, EN" >> ${libname}.xtg
    echo "            EN:  in  STD_LOGIC;" >> vhdldef.sigs
    echo "            EN=>CLK_EN_SIG," >> vhdlins.sigs
    echo "input EN_SIG;" >> verdef.sigs
    echo "            .EN(EN_SIG)," >> verins.sigs
  endif
endif
#
#######################################################
# Write X-BLOX component output pins to component.xtg #
#######################################################
#
if (${p_func} != undefined) then
  echo "             func:  ${p_func}"
  echo "             func:  ${p_func}" >> xbloxgen.log
  if (${p_func} == "yes") then
    echo "PIN, FUNC, O, FUNC" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            FUNC:  out  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            FUNC=>FUNC_BUS," >> vhdlins.sigs
      echo "output [${size}:0] FUNC_BUS;" >> verdef.sigs
      echo "            .FUNC(FUNC_BUS)," >> verins.sigs
    else
      echo "            FUNC:  out  STD_LOGIC;" >> vhdldef.sigs
      echo "            FUNC=>FUNC_SIG," >> vhdlins.sigs
      echo "output FUNC_SIG;" >> verdef.sigs
      echo "            .FUNC(FUNC_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_q_out} != undefined) then
  echo "            q_out:  ${p_q_out}"
  echo "            q_out:  ${p_q_out}" >> xbloxgen.log
  if (${p_q_out} == "yes") then
    echo "PIN, Q_OUT, O, Q_OUT" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            Q_OUT:  out  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            Q_OUT=>Q_OUT_BUS," >> vhdlins.sigs
      echo "output [${size}:0] Q_OUT_BUS;" >> verdef.sigs
      echo "            .Q_OUT(Q_OUT_BUS)," >> verins.sigs
    else
      echo "            Q_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
      echo "            Q_OUT=>Q_OUT_SIG," >> vhdlins.sigs
      echo "output Q_OUT_SIG;" >> verdef.sigs
      echo "            .Q_OUT(Q_OUT_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_par_out} != undefined) then
  echo "          par_out:  ${p_par_out}"
  echo "          par_out:  ${p_par_out}" >> xbloxgen.log
  if (${p_par_out} == "yes") then
    echo "PIN, PAR_OUT, O, PAR_OUT" >> ${libname}.xtg
    if (${size} != "0") then
      echo "            PAR_OUT:  out  STD_LOGIC_VECTOR (${size} downto 0);" >> vhdldef.sigs
      echo "            PAR_OUT=>PAR_OUT_BUS," >> vhdlins.sigs
      echo "output [${size}:0] PAR_OUT_BUS;" >> verdef.sigs
      echo "            .PAR_OUT(PAR_OUT_BUS)," >> verins.sigs
    else
      echo "            PAR_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
      echo "            PAR_OUT=>PAR_OUT_SIG," >> vhdlins.sigs
      echo "output PAR_OUT_SIG;" >> verdef.sigs
      echo "            .PAR_OUT(PAR_OUT_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_d_out} != undefined) then
  echo "            d_out:  ${p_d_out}"
  echo "            d_out:  ${p_d_out}" >> xbloxgen.log
  if (${p_d_out} == "yes") then
    echo "PIN, D_OUT, O, D_OUT" >> ${libname}.xtg
    if (${d_out_size} != "0") then
      echo "            D_OUT:  out  STD_LOGIC_VECTOR (${d_out_size} downto 0);" >> vhdldef.sigs
      echo "            D_OUT=>D_OUT_BUS," >> vhdlins.sigs
      echo "output [${d_out_size}:0] D_OUT_BUS;" >> verdef.sigs
      echo "            .D_OUT(D_OUT_BUS)," >> verins.sigs
    else
      echo "            D_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
      echo "            D_OUT=>D_OUT_SIG," >> vhdlins.sigs
      echo "output D_OUT_SIG;" >> verdef.sigs
      echo "            .D_OUT(D_OUT_SIG)," >> verins.sigs
    endif
  endif
endif
if (${p_clk_out} != undefined) then
  echo "          clk_out:  ${p_clk_out}"
  echo "          clk_out:  ${p_clk_out}" >> xbloxgen.log
  if (${p_clk_out} == "yes") then
    echo "PIN, CLK_OUT, O, CLK_OUT" >> ${libname}.xtg
    echo "            CLK_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            CLK_OUT=>CLK_OUT_SIG," >> vhdlins.sigs
    echo "output CLK_OUT_SIG;" >> verdef.sigs
    echo "            .CLK_OUT(CLK_OUT_SIG)," >> verins.sigs
  endif
endif
if (${p_c_out} != undefined) then
  echo "        carry-out:  ${p_c_out}"
  echo "        carry-out:  ${p_c_out}" >> xbloxgen.log
  if (${p_c_out} == "yes") then
    echo "PIN, C_OUT, O, C_OUT" >> ${libname}.xtg
    echo "            C_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            C_OUT=>C_OUT_SIG," >> vhdlins.sigs
    echo "output C_OUT_SIG;" >> verdef.sigs
    echo "            .C_OUT(C_OUT_SIG)," >> verins.sigs
  endif
endif
if (${p_ms_out} != undefined) then
  echo "           ms_out:  ${p_ms_out}"
  echo "           ms_out:  ${p_ms_out}" >> xbloxgen.log
  if (${p_ms_out} == "yes") then
    echo "PIN, MS_OUT, O, MS_OUT" >> ${libname}.xtg
    echo "            MS_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            MS_OUT=>MS_OUT_SIG," >> vhdlins.sigs
    echo "output MS_OUT_SIG;" >> verdef.sigs
    echo "            .MS_OUT(MS_OUT_SIG)," >> verins.sigs
  endif
endif
if (${p_ls_out} != undefined) then
  echo "           ls_out:  ${p_ls_out}"
  echo "           ls_out:  ${p_ls_out}" >> xbloxgen.log
  if (${p_ls_out} == "yes") then
    echo "PIN, LS_OUT, O, LS_OUT" >> ${libname}.xtg
    echo "            LS_OUT:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            LS_OUT=>LS_OUT_SIG," >> vhdlins.sigs
    echo "output LS_OUT_SIG;" >> verdef.sigs
    echo "            .LS_OUT(LS_OUT_SIG)," >> verins.sigs
  endif
endif
if (${p_ovfl} != undefined) then
  echo "         overflow:  ${p_ovfl}"
  echo "         overflow:  ${p_ovfl}" >> xbloxgen.log
  if (${p_ovfl} == "yes") then
    echo "PIN, OVFL, O, OVFL" >> ${libname}.xtg
    echo "            OVFL:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            OVFL=>OVFL_SIG," >> vhdlins.sigs
    echo "output OVFL_SIG;" >> verdef.sigs
    echo "            .OVFL(OVFL_SIG)," >> verins.sigs
  endif
endif
if (${p_sel_error} != undefined) then
  echo "        sel_error:  ${p_sel_error}"
  echo "        sel_error:  ${p_sel_error}" >> xbloxgen.log
  if (${p_sel_error} == "yes") then
    echo "PIN, SEL_ERROR, O, SEL_ERROR" >> ${libname}.xtg
    echo "            SEL_ERROR:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            SEL_ERROR=>SEL_ERROR_SIG," >> vhdlins.sigs
    echo "output SEL_ERROR_SIG;" >> verdef.sigs
    echo "            .SEL_ERROR(SEL_ERROR_SIG)," >> verins.sigs
  endif
endif
if (${p_term_cnt} != undefined) then
  echo "         term_cnt:  ${p_term_cnt}"
  echo "         term_cnt:  ${p_term_cnt}" >> xbloxgen.log
  if (${p_term_cnt} == "yes") then
    echo "PIN, TERM_CNT, O, TERM_CNT" >> ${libname}.xtg
    echo "            TERM_CNT:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            TERM_CNT=>TERM_CNT_SIG," >> vhdlins.sigs
    echo "output TERM_CNT_SIG;" >> verdef.sigs
    echo "            .TERM_CNT(TERM_CNT_SIG)," >> verins.sigs
  endif
endif
if (${p_a_eq_b} != undefined) then
  echo "           a_eq_b:  ${p_a_eq_b}"
  echo "           a_eq_b:  ${p_a_eq_b}" >> xbloxgen.log
  if (${p_a_eq_b} == "yes") then
    echo "PIN, A_EQ_B, O, A_EQ_B" >> ${libname}.xtg
    echo "            A_EQ_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_EQ_B=>A_EQ_B_SIG," >> vhdlins.sigs
    echo "output A_EQ_B_SIG;" >> verdef.sigs
    echo "            .A_EQ_B(A_EQ_B_SIG)," >> verins.sigs
  endif
endif
if (${p_a_ne_b} != undefined) then
  echo "           a_ne_b:  ${p_a_ne_b}"
  echo "           a_ne_b:  ${p_a_ne_b}" >> xbloxgen.log
  if (${p_a_ne_b} == "yes") then
    echo "PIN, A_NE_B, O, A_NE_B" >> ${libname}.xtg
    echo "            A_NE_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_NE_B=>A_NE_B_SIG," >> vhdlins.sigs
    echo "output A_NE_B_SIG;" >> verdef.sigs
    echo "            .A_NE_B(A_NE_B_SIG)," >> verins.sigs
  endif
endif
if (${p_a_lt_b} != undefined) then
  echo "           a_lt_b:  ${p_a_lt_b}"
  echo "           a_lt_b:  ${p_a_lt_b}" >> xbloxgen.log
  if (${p_a_lt_b} == "yes") then
    echo "PIN, A_LT_B, O, A_LT_B" >> ${libname}.xtg
    echo "            A_LT_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_LT_B=>A_LT_B_SIG," >> vhdlins.sigs
    echo "output A_LT_B_SIG;" >> verdef.sigs
    echo "            .A_LT_B(A_LT_B_SIG)," >> verins.sigs
  endif
endif
if (${p_a_gt_b} != undefined) then
  echo "           a_gt_b:  ${p_a_gt_b}"
  echo "           a_gt_b:  ${p_a_gt_b}" >> xbloxgen.log
  if (${p_a_gt_b} == "yes") then
    echo "PIN, A_GT_B, O, A_GT_B" >> ${libname}.xtg
    echo "            A_GT_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_GT_B=>A_GT_B_SIG," >> vhdlins.sigs
    echo "output A_GT_B_SIG;" >> verdef.sigs
    echo "            .A_GT_B(A_GT_B_SIG)," >> verins.sigs
  endif
endif
if (${p_a_le_b} != undefined) then
  echo "           a_le_b:  ${p_a_le_b}"
  echo "           a_le_b:  ${p_a_le_b}" >> xbloxgen.log
  if (${p_a_le_b} == "yes") then
    echo "PIN, A_LE_B, O, A_LE_B" >> ${libname}.xtg
    echo "            A_LE_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_LE_B=>A_LE_B_SIG," >> vhdlins.sigs
    echo "output A_LE_B_SIG;" >> verdef.sigs
    echo "            .A_LE_B(A_LE_B_SIG)," >> verins.sigs
  endif
endif
if (${p_a_ge_b} != undefined) then
  echo "           a_ge_b:  ${p_a_ge_b}"
  echo "           a_ge_b:  ${p_a_ge_b}" >> xbloxgen.log
  if (${p_a_ge_b} == "yes") then
    echo "PIN, A_GE_B, O, A_GE_B" >> ${libname}.xtg
    echo "            A_GE_B:  out  STD_LOGIC;" >> vhdldef.sigs
    echo "            A_GE_B=>A_GE_B_SIG," >> vhdlins.sigs
    echo "output A_GE_B_SIG;" >> verdef.sigs
    echo "            .A_GE_B(A_GE_B_SIG)," >> verins.sigs
  endif
endif
echo "END" >> ${libname}.xtg
echo ""
#
nawk -F ',[ \t]*' '/^PIN/{printf("SIG, %s, S\n", $4)}' ${libname}.xtg > siglist.tmp
cat miscrecs.tmp >> siglist.tmp
cat siglist.tmp >> ${libname}.xtg
if (${debug} != TRUE) rm -f miscrecs.tmp
if (${debug} != TRUE) rm -f siglist.tmp
echo "EOF" >> ${libname}.xtg
#
goto runblox

#############################
# Run X-BLOX on libname.xtg #
#############################

runblox: 
#
rm -f ${libname}.xg
if ( -e ${libname}.xnf ) then
  echo "    Warning:  The file '${libname}.xnf' already exists."
  echo "              The file will be renamed '${libname}_xnf.bak'."
  echo ""
  echo "    Warning:  The file '${libname}.xnf' already exists." >> xbloxgen.log
  echo "              The file will be renamed '${libname}_xnf.bak'." >> xbloxgen.log
  echo "" >> xbloxgen.log
  mv -f ${libname}.xnf ${libname}_xnf.bak
endif
if ( -e ${libname}.blx ) then
  echo "    Warning:  The file '${libname}.blx' already exists."
  echo "              The file will be renamed '${libname}_blx.bak'."
  echo ""
  echo "    Warning:  The file '${libname}.blx' already exists." >> xbloxgen.log
  echo "              The file will be renamed '${libname}_blx.bak'." >> xbloxgen.log
  echo "" >> xbloxgen.log
  mv -f ${libname}.blx ${libname}_blx.bak
endif
echo "Running X-BLOX to create '${libname}.xnf'."
echo ""
echo "" >> xbloxgen.log
echo "Running X-BLOX to create '${libname}.xnf'." >> xbloxgen.log
echo "" >> xbloxgen.log
xblox ${libname}.xtg archopt=false mergeio=false >> xbloxgen.log
#
if ( -e ${libname}.xg ) then
  sed s/H_SET/HU_SET/g ${libname}.xg > .xbloxgen.tsed1
  awk '{if ($1 != "HIERG,") {print $0}}' .xbloxgen.tsed1 > .xbloxgen.tsed2
  sed s/'[H][I][E][R][G][=][0-9][0-9]*'//g .xbloxgen.tsed2 > ${libname}.xnf
  if (${sel_size} == "0") then
    if (${p_sel} != "undefined") then
      sed s/SEL\<0\>/SEL/g ${libname}.xnf > .xbloxgen.tsed3
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed3 ${libname}.xnf
    endif
  endif
  if (${d_out_size} == "0") then
    if (${p_d_out} != "undefined") then
      sed s/D_OUT\<0\>/D_OUT/g ${libname}.xnf > .xbloxgen.tsed4
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed4 ${libname}.xnf
    endif
  endif
  if (${size} == "0") then
    if (${p_a} != "undefined") then
      sed s/A\<0\>/A/g ${libname}.xnf > .xbloxgen.tsed5
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed5 ${libname}.xnf
    endif
    if (${p_b} != "undefined") then
      sed s/B\<0\>/B/g ${libname}.xnf > .xbloxgen.tsed6
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed6 ${libname}.xnf
    endif
    if (${p_d_in} != "undefined") then
      sed s/D_IN\<0\>/D_IN/g ${libname}.xnf > .xbloxgen.tsed7
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed7 ${libname}.xnf
    endif
    if (${p_par_in} != "undefined") then
      sed s/PAR_IN\<0\>/PAR_IN/g ${libname}.xnf > .xbloxgen.tsed8
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed8 ${libname}.xnf
    endif
    if (${p_func} != "undefined") then
      sed s/FUNC\<0\>/FUNC/g ${libname}.xnf > .xbloxgen.tsed9
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed9 ${libname}.xnf
    endif
    if (${p_q_out} != "undefined") then
      sed s/Q_OUT\<0\>/Q_OUT/g ${libname}.xnf > .xbloxgen.tsed10
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed10 ${libname}.xnf
    endif
    if (${p_par_out} != "undefined") then
      sed s/PAR_OUT\<0\>/PAR_OUT/g ${libname}.xnf > .xbloxgen.tsed11
      rm -f ${libname}.xnf
      cp .xbloxgen.tsed11 ${libname}.xnf
    endif
  endif
  if (-e ${libname}.xnf) then
    mv ${libname}.xnf .xbloxgen.tsed12
    awk '{if ($1 != "PROG," || $2 != "XBLOX,") {print $0}}' .xbloxgen.tsed12 > ${libname}.xnf
  endif
  if (${debug} != TRUE) rm -f ${libname}.xg
  if (${debug} != TRUE) rm -f ${libname}.xtg
  if (${debug} != TRUE) rm -f xblox.log
  echo "The file '${libname}.xnf' has been successfully created."
  echo ""
  echo "" >> xbloxgen.log
  echo "The file '${libname}.xnf' has been successfully created." >> xbloxgen.log
  echo "" >> xbloxgen.log
  set vhdlw = undefined
  set verilogw = undefined
  if ((${vhdl} == undefined) || (${verilog} == undefined)) then
    echo "VHDL and Verilog example files can be created containing"
    echo "the necessary code to instantiate ${libname}.xnf."
    echo ""
  endif
  #
  createcompfiles:
  #
  if (${vhdl} == undefined) then
    goto createvhdl
  endif
  if (${verilog} == undefined) then
   goto createverilog
  endif
  if ((${vhdlw} == undefined) && ($vhdl == "yes")) then
    goto write_vhdlex
  endif
  if ((${verilogw} == undefined) && ($verilog == "yes")) then
    goto write_verilogex
  endif
else
  echo "    ERROR:  The file '${libname}.xnf' was NOT created.  Please check"
  echo "            the output file '${libname}.xbg' for more information."
  echo ""
  echo "" >> xbloxgen.log
  echo "    ERROR:  The file '${libname}.xnf' was NOT created.  Please check" >> xbloxgen.log
  echo "            the output file 'xbloxgen.xbg' for more information." >> xbloxgen.log
  echo "" >> xbloxgen.log
endif
echo "Saving log file 'xbloxgen.log' to file '${libname}.xbg'."
echo ""
if ( -e ${libname}.xbg ) then
  echo "    Warning:  The file '${libname}.xbg' already exists."
  echo "              The file will be renamed '${libname}_xbg.bak'."
  echo ""
  echo "    Warning:  The file '${libname}.xbg' already exists." >> xbloxgen.log
  echo "              The file will be renamed '${libname}_xbg.bak'." >> xbloxgen.log
  echo "" >> xbloxgen.log
  mv -f ${libname}.xbg ${libname}_xbg.bak
endif
mv -f xbloxgen.log ${libname}.xbg
echo "Would you like to create another component?"
echo -n "Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == "y") || (${resp} == "Y")) then
  set comptype = undefined
  set vhdl = undefined
  set verilog = undefined
  goto getcomptype
else
  goto end
endif

#########################
# Get Smallest Parttype #
#########################

getparttype:
#
echo "  The following is a list of device types"
echo "  that have been found in your system:"
echo ""
foreach f (${dis_devices})
  echo "    ${f}"
end
echo ""
echo "  What is the SMALLEST device the ${comptype}"
echo "  '${libname}' will be used in?"
echo -n "  Enter device number (or 'q' to quit):  "
set resp = $<
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
else
  set chosen = "none"
  set counti = 0
  foreach f (${dis_devices})
    @ counti = $counti + 1
    if (${f} == ${resp}) then
      set choseni = ${counti}
      set chosen = ${f}
    endif
  end
  if (${chosen} != "none") then
    set tempi = 1
    foreach h (${found_devices})
      if (${tempi} == ${choseni}) then
        set chosenpkg = $h
      endif
      @ tempi = $tempi + 1
    end
  else
    echo ""
    echo "    Error:  The specified device '${resp}' is not supported"
    echo "            by your current software setup."
    echo ""
    echo "" >> xbloxgen.log
    echo "    Error:  The specified device '${resp}' is not supported" >> xbloxgen.log
    echo "            by your current software setup." >> xbloxgen.log
    echo "" >> xbloxgen.log
    goto getparttype
  endif
endif
echo ""
goto generate_partreturn

###################################
# ***** Write Example Files ***** #
###################################

######################
# Write VHDL Example #
######################

write_vhdlex:
echo "Generating VHDL example in file '${libname}.vhd'."
echo ""
echo "Generating VHDL example in file '${libname}.vhd'." >> xbloxgen.log
echo "" >> xbloxgen.log
if ( -e ${libname}.vhd ) then
  echo "    Warning:  The file '${libname}.vhd' already exists."
  echo "              The file will be renamed '${libname}_vhd.bak'."
  echo ""
  echo "    Warning:  The file '${libname}.vhd' already exists." >> xbloxgen.log
  echo "              The file will be renamed '${libname}_vhd.bak'." >> xbloxgen.log
  echo "" >> xbloxgen.log
  mv -f ${libname}.vhd ${libname}_vhd.bak
endif
#
rm -f vhdldef.sigs2
rm -f vhdlins.sigs2
touch -f ${libname}.vhd
touch -f vhdldef.sigs2
touch -f vhdlins.sigs2
#
echo "-- The following code is a VHDL example of how to instantiate" >> ${libname}.vhd
echo "-- the ${comptype} '${libname}' you have created." >> ${libname}.vhd
echo "--" >> ${libname}.vhd
echo "-- The component declaration:" >> ${libname}.vhd
echo "--" >> ${libname}.vhd
echo "    component ${libname}" >> ${libname}.vhd
echo "        port (" >> ${libname}.vhd
set vhdldeflen = `wc -l vhdldef.sigs`
set vhdldeflen = `echo ${vhdldeflen} | awk '{print $1}'`
@ vhdldeflen = ${vhdldeflen} - 1
head -${vhdldeflen} vhdldef.sigs > vhdldef.sigs2
sed s/\;//g vhdldef.sigs | tail -1 >> vhdldef.sigs2
mv -f vhdldef.sigs2 vhdldef.sigs
cat vhdldef.sigs >> ${libname}.vhd
echo "            );" >> ${libname}.vhd
echo "    end component;" >> ${libname}.vhd
echo "--" >> ${libname}.vhd
echo "-- The component instantiation:" >> ${libname}.vhd
echo "--"  >> ${libname}.vhd
echo "        U0:  ${libname} port map (" >> ${libname}.vhd
set vhdlinslen = `wc -l vhdlins.sigs | awk '{print $1}'`
@ vhdlinslen = ${vhdlinslen} - 1
head -${vhdlinslen} vhdlins.sigs > vhdlins.sigs2
sed s/,//g vhdlins.sigs | tail -1 >> vhdlins.sigs2
mv -f vhdlins.sigs2 vhdlins.sigs
cat vhdlins.sigs >> ${libname}.vhd
echo "            );" >> ${libname}.vhd
if (${debug} != TRUE) rm -f vhdldef.sigs
if (${debug} != TRUE) rm -f vhdlins.sigs
cat ${libname}.vhd
cat ${libname}.vhd >> xbloxgen.log
echo ""
set vhdlw = yes
goto createcompfiles

#########################
# Write Verilog Example #
#########################

write_verilogex:
#
echo "Generating Verilog example in file '${libname}.v'."
echo ""
echo "Generating Verilog example in file '${libname}.v'." >> xbloxgen.log
echo "" >> xbloxgen.log
if ( -e ${libname}.v ) then
  echo "    Warning:  The file '${libname}.v' already exists."
  echo "              The file will be renamed '${libname}_v.bak'."
  echo ""
  echo "    Warning:  The file '${libname}.v' already exists." >> xbloxgen.log
  echo "              The file will be renamed '${libname}_v.bak'." >> xbloxgen.log
  echo "" >> xbloxgen.log
  mv -f ${libname}.v ${libname}_v.bak
endif
#
rm -f verins.sigs2
touch -f ${libname}.v
touch -f verins.sigs2
# 
echo "// The following code is a Verilog example of how to instantiate" >> ${libname}.v
echo "// the ${comptype} '${libname}' you have created." >> ${libname}.v
echo "//" >> ${libname}.v
echo "// The signal declarations:" >> ${libname}.v
echo "//" >> ${libname}.v
set verdeflen = `wc -l verdef.sigs`
cat verdef.sigs >> ${libname}.v
echo "//" >> ${libname}.v
echo "// The component instantiation:" >> ${libname}.v
echo "//"  >> ${libname}.v
echo "        ${libname} U0 (" >> ${libname}.v
set verinslen = `wc -l verins.sigs | awk '{print $1}'`
@ verinslen = ${verinslen} - 1
head -${verinslen} verins.sigs > verins.sigs2
sed s/,//g verins.sigs | tail -1 >> verins.sigs2
mv -f verins.sigs2 verins.sigs
cat verins.sigs >> ${libname}.v
echo "            );" >> ${libname}.v
if (${debug} != TRUE) rm -f verdef.sigs
if (${debug} != TRUE) rm -f verins.sigs
cat ${libname}.v
cat ${libname}.v >> xbloxgen.log
echo ""
set verilogw = yes
goto createcompfiles

#################
# VHDL Question #
#################

createvhdl:
#
echo "  Would you like to have a VHDL file created?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
else
  if ((${resp} == 'y') || (${resp} == 'Y')) then
    set vhdl = yes
  else
    if ((${resp} == 'n') || (${resp} == 'N')) then
      set vhdl = no
    else
      echo "    Error:  The entry '${resp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto createvhdl
    endif
  endif
endif    
goto createcompfiles

####################
# Verilog Question #
####################

createverilog:
#
echo "  Would you like to have a Verilog file created?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
else
  if ((${resp} == 'y') || (${resp} == 'Y')) then
    set verilog = yes
  else
    if ((${resp} == 'n') || (${resp} == 'N')) then
      set verilog = no
    else
      echo "    Error:  The entry '${resp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto createverilog
    endif
  endif
endif    
goto createcompfiles

##############################################
# ***** Define General Characteristics ***** #
##############################################

###################
# Define genericp #
###################

define_genericp:
#
echo "  Will the ${pintoget} ${direction} be needed?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
else
  if ((${resp} == 'y') || (${resp} == 'Y')) then
    set p_${pintoget} = yes
  else 
    if ((${resp} == 'n') || (${resp} == 'N')) then
      set p_${pintoget} = no
    else
      echo "    Error:  The entry '${resp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto define_genericp
    endif
  endif
endif
goto setchar_${comptype}

######################
# Get component name #
######################

define_libname:
#
echo -n "  Enter the name of the ${comptype}:  "
set libname = $<
echo ""
if ( ${libname} == "" ) then
  echo "    Error:  Ivalid filename."
  echo ""
  goto define_libname
endif
set libname = ${libname:r}
goto setchar_${comptype}

###############
# Define size #
###############

define_size:
#
echo "  Enter the number of bits of the ${comptype}"
echo -n "  (or 'q' to quit):  "
set size = $< 
echo ""
if ( ${size} == 'q' || ${size} == 'Q' ) then
  goto end
else
  set checksize = `echo ${size} | grep -v '[^0-9]'`
  if (( ${checksize} != ${size} ) \
	|| ( ${size} == "" ) \
	|| ( ${size} == 0 )) then
    echo "    Error:  The entry '${size}' is invalid."
    echo "            The size must be a positive integer."
    echo ""
    goto define_size
  else    
    @ size = ${size} - 1
  endif
endif
goto setchar_${comptype}

###################
# Define sel size #
###################

define_sel_size:
#
echo "  Enter the number of bits in the SEL bus"
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  set checkresp = `echo ${resp} | grep -v '[^0-9]'`
  if (( ${checkresp} != ${resp} ) \
	|| ( ${resp} == "" ) \
	|| ( ${resp} == 0 )) then
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The size must be a positive integer."
    echo ""
    goto define_sel_size
  else    
    @ sel_size = ${resp} - 1
  endif
endif
goto setchar_${comptype}

#####################
# Define d_out size #
#####################

define_d_out_size:
#
echo "  Enter the number of bits in the D_OUT bus"
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  set checkresp = `echo ${resp} | grep -v '[^0-9]'`
  if (( ${checkresp} != ${resp} ) \
	|| ( ${resp} == "" ) \
	|| ( ${resp} == 0 )) then
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The size must be a positive integer."
    echo ""
    goto define_d_out_size
  else    
    @ d_out_size = ${resp} - 1
  endif
endif
goto setchar_${comptype}

#########################
# Define arith encoding #
#########################

define_aencoding:
#
echo "  The available arithemetic bus encodings are:"
echo ""
echo "          1)  UBIN"
echo "          2)  TWO_COMP"
echo ""
echo "  Enter the number of the desired encoding"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
switch (${resp})
  case 1:
    set encoding = UBIN
    breaksw
  case 2:
    set encoding = TWO_COMP
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 and 2."
    echo ""
    goto define_aencoding
    breaksw
endsw
goto setchar_${comptype}

############################
# Define standard encoding #
############################

define_sencoding:
#
echo "  The available standard bus encodings are:"
echo ""
echo "          1)  UBIN"
echo "          2)  ONE_HOT"
echo "          3)  TWO_COMP"
echo ""
echo "  Enter the number of the desired encoding"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
switch (${resp})
  case 1:
    set encoding = UBIN
    breaksw
  case 2:
    set encoding = ONE_HOT
    breaksw
  case 3:
    set encoding = TWO_COMP
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 and 3."
    echo ""
    goto define_sencoding
    breaksw
endsw
goto setchar_${comptype}

#######################
# Define SEL encoding #
#######################

define_selencoding:
#
echo "  The available SEL bus encodings are:"
echo ""
echo "          1)  UBIN"
echo "          2)  ONE_HOT"
echo "          3)  TWO_COMP"
echo ""
echo "  Enter the number of the desired encoding"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
switch (${resp})
  case 1:
    set selencoding = UBIN
    breaksw
  case 2:
    set selencoding = ONE_HOT
    breaksw
  case 3:
    set selencoding = TWO_COMP
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 and 3."
    echo ""
    goto define_selencoding
    breaksw
endsw
goto setchar_${comptype}

##############################
# ***** Define Pin Use ***** #
##############################

###################
# Define p_addsub #
###################

define_addsubp:
#
echo "  The available ${comptype} arithemetic operations are:"
echo ""
echo "          1)  ADD (default)"
echo "          2)  SUB"
echo "          3)  ADD/SUB"
echo ""
echo "  Enter the number of the desired operation (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 1
endif
switch (${resp})
  case 1:
    set p_addsub = ADD
    breaksw
  case 2:
    set p_addsub = SUB
    breaksw
  case 3:
    set p_addsub = ADD_SUB
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_addsubp
    breaksw
endsw
goto setchar_${comptype}

####################
# Define p_inc_dec #
####################

define_inc_decp:
#
echo "  The available ${comptype} arithemetic operations are:"
echo ""
echo "          1)  INC (default)"
echo "          2)  DEC"
echo "          3)  INC/DEC"
echo ""
echo "  Enter the number of the desired operation (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 1
endif
switch (${resp})
  case 1:
    set p_inc_dec = INC
    breaksw
  case 2:
    set p_inc_dec = DEC
    breaksw
  case 3:
    set p_inc_dec = INC/DEC
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_inc_decp
    breaksw
endsw
goto setchar_${comptype}

###################
# Define p_up_dnp #
###################

define_up_dnp:
#
echo "  The available ${comptype} directions are:"
echo ""
echo "          1)  UP (default)"
echo "          2)  DOWN"
echo "          3)  UP/DOWN"
echo ""
echo "  Enter the number of the desired direction (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 1
endif
switch (${resp})
  case 1:
    set p_up_dn = UP
    breaksw
  case 2:
    set p_up_dn = DOWN
    breaksw
  case 3:
    set p_up_dn = UP/DOWN
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_up_dnp
    breaksw
endsw
goto setchar_${comptype}

#######################
# Define p_right_left #
#######################

define_right_leftp:
#
echo "  The available ${comptype} directions are:"
echo ""
echo "          1)  RIGHT"
echo "          2)  LEFT"
echo "          3)  RIGHT/LEFT"
echo ""
echo "  Enter the number of the desired direction"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
switch (${resp})
  case 1:
    set p_right_left = RIGHT
    breaksw
  case 2:
    set p_right_left = LEFT
    breaksw
  case 3:
    set p_right_left = RIGHT/LEFT
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_right_leftp
    breaksw
endsw
goto setchar_${comptype}

#################
# Define p_load #
#################

define_loadp:
#
echo "  Will the ${comptype} be loadable?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
else
  if ((${resp} == 'y') || (${resp} == 'Y')) then
    set p_load = yes
  else 
    if ((${resp} == 'n') || (${resp} == 'N')) then
      set p_load = no
    else
      echo "    Error:  The entry '${resp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto define_loadp
    endif
  endif
endif
goto setchar_${comptype}

#################
# Define asyncp #
#################

define_asyncp:
#
echo "  Will an asynchronous control be needed?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set asyncp = $<
echo ""
if ((${asyncp} == 'q') || (${asyncp} == 'Q')) then
  goto end
else
  if ((${asyncp} == 'y') || (${asyncp} == 'Y')) then
    set asyncp = yes
    #
    if (${a_asyncval} == undefined) then
      goto define_asyncvala
      define_asyncpr:
    endif
    #
  else 
    if ((${asyncp} == 'n') || (${asyncp} == 'N')) then
      set asyncp = no
    else
      echo "    Error:  The entry '${asyncp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto define_asyncp
    endif
  endif
endif
goto setchar_${comptype}

#############################
# Define asyncval Attribute #
#############################

define_asyncvala:
#
echo "  Enter the asynchronous value (return for default 0)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if (("${resp}" == 'q') || ("${resp}" == 'Q')) then
  goto end
endif
if ("${resp}" == "") then
  set a_asyncval = 0
else
  set a_asyncval = ${resp}
endif
goto define_asyncpr

################
# Define syncp #
################

define_syncp:
#
echo "  Will a synchronous control be needed?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set syncp = $<
echo ""
if ((${syncp} == 'q') || (${syncp} == 'Q')) then
  goto end
else
  if ((${syncp} == 'y') || (${syncp} == 'Y')) then
    set syncp = yes
    #
    if (${a_syncval} == undefined) then
      goto define_syncvala
      define_syncpr:
    endif
    #
    if ((${a_syncval} == 'q') || (${a_syncval} == 'Q')) then
      goto end
    endif
  else 
    if ((${syncp} == 'n') || (${syncp} == 'N')) then
      set syncp = no
    else
      echo "    Error:  The entry '${syncp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto define_syncp
    endif
  endif
endif
goto setchar_${comptype}

############################
# Define syncval Attribute #
############################

define_syncvala:
#
echo "  Enter the synchronous value (return for default 0)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if (("${resp}" == 'q') || ("${resp}" == 'Q')) then
  goto end
endif
if ("${resp}" == "") then
  set a_syncval = 0
else
  set a_syncval = ${resp}
endif
goto define_syncpr

#################################
# ***** Define Attributes ***** #
#################################

#############################
# Define aristyle Attribute #
#############################

define_aristylea:
#
echo "  The available ${comptype} implementation styles are:"
echo ""
echo "          1)  ALIGNED (default)"
echo "          2)  UNALIGNED"
echo "          3)  RIPPLE"
echo ""
echo "  Enter the number of the desired style (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 1
endif
switch (${resp})
  case 1:
    set a_aristyle = ALIGNED
    breaksw
  case 2:
    set a_aristyle = UNALIGNED
    breaksw
  case 3:
    set a_aristyle = RIPPLE
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_aristylea
    breaksw
endsw
goto setchar_${comptype}

#############################
# Define comstyle Attribute #
#############################

define_comstylea:
#
echo "  The available COMPARE implementation styles are:"
echo ""
echo "          1)  ARITH"
echo "          2)  TREE"
echo "          3)  WIRED"
echo "          4)  RIPPLE"
echo "          5)  Allow X-BLOX to determine style (default)"
echo ""
echo "  Enter the number of the desired style (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 5
endif
switch (${resp})
  case 1:
    set a_comstyle = ARITH
    breaksw
  case 2:
    set a_comstyle = TREE
    breaksw
  case 3:
    set a_comstyle = WIRED
    breaksw
  case 4:
    if ((${p_a_lt_b} == "no") && (${p_a_gt_b} == "no") && (${p_a_le_b} == "no") && (${p_a_ge_b} == "no")) then
      set a_comstyle = RIPPLE
    else
      echo "    Error:  The style 'RIPPLE' cannot be used when"
      echo "            computing:  a_lt_b, a_gt_b, a_le_b, a_ge_b"
      echo "            Please select another style."
      echo ""
      goto define_comstylea
    endif
    breaksw
  case 5:
    set a_comstyle = XBLOX
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_comstylea
    breaksw
endsw
goto setchar_${comptype}

#############################
# Define sftstyle Attribute #
#############################

define_sftstylea:
#
echo "  The available SHIFT implementation styles are:"
echo ""
echo "          1)  LOGICAL (default)"
echo "          2)  CIRCULAR"
echo "          3)  ARITH"
echo ""
echo "  Enter the number of the desired style (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 1
endif
switch (${resp})
  case 1:
    set a_sftstyle = LOGICAL
    breaksw
  case 2:
    if ((${p_ms_in} == "no") && (${p_ls_in} == "no")) then
      set a_sftstyle = CIRCULAR
    else
      echo "    Error:  The CIRCULAR style cannot be used when"
      echo "            either MS_IN or LS_IN are connected."
      echo ""
      goto define_sftstylea
    endif
    breaksw
  case 3:
    set a_sftstyle = ARITH
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 3."
    echo ""
    goto define_sftstylea
    breaksw
endsw
goto setchar_${comptype}

#############################
# Define coustyle Attribute #
#############################

define_coustylea:
#
echo "  The available COUNTER implementation styles are:"
echo ""
echo "          1)  BINARY"
echo "          2)  JOHNSON"
echo "          3)  LFSR"
echo "          4)  ONE_HOT"
echo "          5)  Allow X-BLOX to determine style (default)"
echo ""
echo "  Enter the number of the desired style (return for default)"
echo -n "  (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto end
endif
if (${resp} == "") then
  set resp = 5
endif
switch (${resp})
  case 1:
    set a_coustyle = BINARY
    breaksw
  case 2:
    set a_coustyle = JOHNSON
    breaksw
  case 3:
    set a_coustyle = LFSR
    breaksw
  case 4:
    set a_coustyle = ONE_HOT
    breaksw
  case 5:
    set a_coustyle = XBLOX
    breaksw
  default:
    echo "    Error:  The entry '${resp}' is invalid."
    echo "            The valid entries are 1 through 4."
    echo ""
    goto define_coustylea
    breaksw
endsw
goto setchar_${comptype}

############################
# Define countto Attribute #
############################

define_counttoa:
#
echo "  Enter the COUNT_TO value (return for max count)"
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  if (${resp} == "") then
    set a_countto = max
  else
    set a_countto = ${resp}
  endif
endif
goto setchar_${comptype}

###########################
# Define inc_by Attribute #
###########################

define_inc_bya:
#
echo "  Enter the ${p_inc_dec} value (return for 1)"
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  if (${resp} == "") then
    set a_inc_by = 1
  else
    set a_inc_by = ${resp}
  endif
endif
goto setchar_${comptype}

##############################
# Define divide_by Attribute #
##############################

define_divide_bya:
#
echo "  Enter the DIVIDE_BY value"
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  if (${resp} == "") then
    echo "    Error:  A DIVIDE_BY value must be entered."
    echo ""
    goto define_divide_bya
  else
    set a_divide_by = ${resp}
  endif
endif
goto setchar_${comptype}

###############################
# Define duty_cycle Attribute #
###############################

define_duty_cyclea:
#
echo "  The DUTY CYCLE of the X-BLOX CLK_DIV is defined"
echo "  by specifying the number of cycles the output will"
echo "  be high."
echo ""
echo "  Enter the number of cycles the output will be high."
echo "  Hit return for 1/2 DIVIDE BY value."
echo -n "  (or 'q' to quit):  "
set resp = $< 
echo ""
if ( ${resp} == 'q' || ${resp} == 'Q' ) then
  goto end
else
  if (${resp} == "") then
    set a_duty_cycle = "HALF DIVIDE_BY"
  else
    set a_duty_cycle = ${resp}
  endif
endif
goto setchar_${comptype}

#########################
# Define rloc Attribute #
#########################

define_rloca:
#
echo "  Should an RLOC be generated?"
echo -n "  Enter 'y' or 'n' (or 'q' to quit):  "
set resp = $<
echo ""
if ((${resp} == 'q') || (${resp} == 'Q')) then
  goto exit
else
  if ((${resp} == 'y') || (${resp} == 'Y')) then
    set a_rloc = TRUE
  else 
    if ((${resp} == 'n') || (${resp} == 'N')) then
      set a_rloc = FALSE
    else
      echo "    Error:  The entry '${resp}' is invalid."
      echo "            The valid entries are 'y' and 'n'."
      echo ""
      goto define_rloca
    endif
  endif
endif
goto setchar_${comptype}

##############################
# Initialize characteristics #
##############################

initchars:
  # General variables
  set libname = undefined
  set size = undefined
  set sel_size = undefined
  set d_out_size = undefined
  set encoding = undefined
  set selencoding = undefined
  # Inputs
  set inputs = "p_sel p_inc_dec p_en p_par_in p_right_left p_ms_in p_ls_in p_a p_b p_d_in p_clk p_addsub p_up_dn p_c_in p_clk_en p_load asyncp syncp"
  foreach f (`echo ${inputs}`)
    set $f = undefined
  end
  # Outputs
  set outputs = "p_d_out p_sel_error p_q_out p_func p_c_out p_ovfl p_term_cnt p_a_eq_b p_a_ne_b p_a_lt_b p_a_gt_b p_a_le_b p_a_ge_b p_par_out p_ls_out p_ms_out p_clk_out"
  foreach f (`echo $outputs`)
    set $f = undefined
  end
  # Attributes
  set attributes = "a_asyncval a_syncval a_aristyle a_comstyle a_coustyle a_countto a_rloc a_sftstyle a_divide_by a_duty_cycle a_inc_by"
  foreach f (`echo $attributes`)
    set $f = undefined
  end
goto setchar_${comptype}

parse_params:
  foreach f (${argv})
    switch (${f})
      case "-vhdl":
        set vhdl = yes
        if (${verilog} == undefined) then
          set verilog = no
        endif
      breaksw
      case "-ver":
        set verilog = yes
        if (${vhdl} == undefined) then
          set vhdl = no
        endif
      breaksw
      case "-help":
        goto displayhelp
      breaksw
      case "-h":
        goto displayhelp
      breaksw
      case "-list":
        goto displayvcomps
      breaksw
      default:
        set dash = `echo ${f} | cut -c1 | grep -c '-'`
        if (${dash} == 1) then
          echo ""
          echo "    Warning:  The parameter '${f}' is illegal,"
          echo "              it will be ignored."
          echo ""
        else
          set clcomp = `echo "$f" | tr '[a-z]' '[A-Z]'`
          set valid = 0
          set index = 0
          foreach f (${validcomps})
            @ index = $index + 1
            if (${f} == ${clcomp}) then
              set valid = $index
            endif
          end
          unset index
          if (${valid} == 0) then
            echo ""
            echo "    Error:  The X-BLOX module '${clcomp}' is invalid."
            goto displayvcomps
          else
            set comptype = $valid
          endif
        endif
      breaksw
    endsw
  end
goto lookforblox

displayhelp:
#
echo "Usage:  xbloxgen [X-BLOX module] [options]"
echo ""
echo "Description:"
echo "  XBLOXGEN is a Xilinx utility that creates XNF files of X-BLOX"
echo "  modules for instantiation into both VHDL and Verilog designs."
echo ""
echo "Required software:"
echo "  The program 'xblox' is used to create the XNF files.  Make sure"
echo "  that xblox is set up before running XBLOXGEN."
echo ""
echo "  The data files found in the DS502 are used by xblox to create"
echo "  the XNF files.  Make sure that the DS502 is set up before"
echo "  running XBLOXGEN."
echo ""
echo "Options:"
echo "  -help => displays this message."
echo "  -list => list the supported X-BLOX modules"
echo "  -ver  => create a sample verilog file"
echo "  -vhdl => create a sample vhdl file"
echo ""
goto exit

displayvcomps:
#
echo ""
echo "The X-BLOX modules supported by xbloxgen are:"
foreach f (${validcomps})
  echo "     ${f}"
end
echo ""
goto exit

end:
echo ""
if (${debug} == "FALSE") then
  echo -n "Cleaning"
  if ( ${?libname} ) then
    if ( -e ${libname}.xbg ) then
      rm -f xbloxgen.log
      echo -n "."
    endif
  endif
  rm -f .xbloxgen.tsed1
  echo -n "."
  rm -f .xbloxgen.tsed2
  echo -n "."
  rm -f .xbloxgen.tsed3
  echo -n "."
  rm -f .xbloxgen.tsed4
  echo -n "."
  rm -f .xbloxgen.tsed5
  echo -n "."
  rm -f .xbloxgen.tsed6
  echo -n "."
  rm -f .xbloxgen.tsed7
  echo -n "."
  rm -f .xbloxgen.tsed8
  echo -n "."
  rm -f .xbloxgen.tsed9
  echo -n "."
  rm -f .xbloxgen.tsed10
  echo -n "."
  rm -f .xbloxgen.tsed11
  echo -n "."
  rm -f .xbloxgen.tsed12
  echo -n "."
  rm -f miscrecs.tmp
  echo -n "."
  rm -f siglist.tmp
  echo -n "."
  rm -f verdef.sigs
  echo -n "."
  rm -f verins.sigs
  echo -n "."
  rm -f vhdldef.sigs
  echo -n "."
  rm -f vhdlins.sigs
  echo -n "."
  rm -f xblox.log
  echo "DONE"
  echo ""
endif
if ((${?libname}) && (${debug} == "FALSE")) then
  rm -f ${libname}.xtg
endif
echo "Goodbye"
echo ""

exit:





