X-VHDL v2.4.4 Enhancements/Corrections List

The following listing shows enhancements and bug fixes that have been made in the X-
VHDL compiler since version 2.3.6, which shipped with Foundation 6.0.1. 

1. Added UI progress bar (on Win3.1, requires win32s 1.3).
2. Added UI menu item to hide transcript window.
3. Added attribute 'ungroup', selectively flattens hierarchy under user control. Allows 
better optimization when hierarchy elements contain little logic.
4. Improved macrocell usage for compares, adders, subtractors, up-down counters.
5. Added LPM 201 package (macros201) to lpm.vhd, existing package 'macros' renamed 
to 'macros200'. Added attribute lpmtype.
6. Added an Index in the documentation. Added new features, and some discussion on 
compile methodology.
7. Added extra text to message 525 for clarity.
8. Extended semantics of 'macrocell attribute. Previously only applied to XBLOX/LPM 
declarations. Now applies to any silicon specific component with bus ports; resulting 
pins do not have underbar between name and index.
9. Added attribute 'numeric_to_array'; complements existing attribute array_to_numeric; 
for speeding up certain type conversion functions.
10. Add support of macrocell attribute at top level entity, this allows support of the bus 
naming convention used by some schematic tools (e.g. "bus#"). This is the same 
convention as is used when 'macrocell is applied to a child component. 
11. Now flushes text to log file more frequently.
12. The AcrobatO file vhdl_mug.pdf  is no longer required for X-VHDL to function.
13. Now writes a file named metamor.end containing an exit status code.
14. Error messages 515 & 516 have been improved and extra explanation added in the 
help file.
15. Compile time improvement when design has wide tristate data path and complex 
enable logic.
16. Fixed incorrect inference of X-BLOX counter module when the following conditions 
exist: (a) counter is described, and (b) the output of the incrementer within the counter 
is used not only by the counter's flip-flops but also by other design logic.
17. Removed the design size constraint on the 50 demo execution limit. 
18. Fixed a problem when compiling for 5k and using a startup symbol.
19. Fixed multiplier operator behavior when one argument is an array constant.
20. Improvement of multiplier in numeric_std and numeric_bit packages.
21. Added Attribute passing to netlist from entity, component, component instance label, 
register, port, signals marked as 'critical, and tristate signals.
22. Added Attribute 'inhibit_buf'. Attach this attribute to a top level port to inhibit 
automatic I/O buffer insertion on that port.
23. Added message 480.
24. Simple latches are now written as RAM for 4k, 4ke.
25. Improved usage of vhdl signal names in XNF.
26. Included hierarchy character '/' in XNF names
27. Added INIT=R/S on XNF ff/lat 4k,4ke in addition to PRE or CLR pins.
28. Added  INFF,INLAT direct inbuf signal path.
29. Now allows instantiation of unbound components driving internal tristate busses.
30. XC5000: when optimize level is zero, components generated now have a maximum of 
4 inputs.
  
