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| XILINX APPLICATIONS XAPP003V:  CFSD12-V2.00               BN-3-18-94  |
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README file for the XC3000A Counter CFSD12:
===========================================

Note: A more detailed description of this application can be found in 
Section 8 of the Xilinx Data Book.


CFSD12
------

  This counter is a 12-bit Loadable Down Counter/Rate Divider.  It is called a
rate divider because it reloads the state on the D inputs when the terminal 
count of all ones is reached.  The counter has a PRESET input to force the 
counter to load the current state on the D inputs. All signals are active-High 
except for the TCB (terminal count).  

  The operation of the counter is based on 2-bit count cells in a single CLB.  
Each of the cells receives two T inputs, Tn and Tn+1, that tell the Qn and 
Qn+1 bits whether to toggle.  Each cell also has two D inputs, Dn and Dn+1, to 
be used when the counter is being reloaded or preset via the TCB input.  

  Parallel decoding is done on the Q0 through Q11 bits in additional CLBs to 
produce the toggle lines T2 through T11 and TCB. The TCB signal is pipelined 
by one register and hence decodes the state of 001 hex.  This allows the 
TCB line to be routed without the burden of an additional CLB delay.  
Also because of this the counter can not be reloaded or preset to 000 hex.  
For a D0 through D11 value of N the TCB line will go low for one clock cycle 
every N+1 clock cycles.

  This counter will at 36 MHz in the XC3000A-6, and at 52 MHz in the 
XC3100A-3.

Design files included in directory CFSD12:

  README         This README file
  SCH\CFSD12H.1  Top-level Viewlogic V4.1.3a schematic
  SCH\CFSD12.1   12 Bit Presettable Down Counter            (Sheet 1)
  SCH\CFSD12.2   CLBMAPs for the counter                    (Sheet 2)
  SYM\*.1        Viewlogic Symbol for Counter
  WIR\*.1        Viewlogic Wire files

  XNF\           Xilinx Netlists for High Level Schematic
  CFSD12H.LCA    Placed and Routed LCA file
  CFSD12H.CST    Contraints file for the CLB placement.
  CFSD12H.XRP    Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Recommended Layout, Routing:

   Simple floorplanning will significantly improve the performance of any 
design. For this counter, the CFSTA/T04Q01-04 CLB should be placed close 
to the Q00_01, Q02_03, and Q04_05 CLBs. The CFSTA/(Q5-7-8, Q5-9-11, T10_11), 
and TCB CLBs should be placed just below this in the column to the right of 
the count CLBs.  The other CLBs should be placed top to bottom in order of 
rank just to the right of the already placed CLBs.

This placement is listed below:

place block Q0 : AA;
place block Q2 : BA;
place block Q4 : CA;
place block Q6 : DA;
place block Q8 : EA;
place block Q10 : FB;
place block CFSTA/T2 : AB;
place block CFSTA/T4 : BB;
place block CFSTA/Q5-7 : CB;
place block CFSTA/Q5-9 : DB;
place block CFSTA/T10 : EB;
place block CFSTA/T5 : CC;
place block CFSTA/T6 : DC;
place block CFSTA/T8 : EC;
place block TCB : FC;


   For maximum performance, some hand routing may be required, although PPR 
will do a very good job on longline assignment and the use of zero delay
routing resources.
 
   The recommended routing is now described.  The longest logic path is
from the Q5 - Q8 bits through the CFSTA/Q5-7-8 CLB through the
CFSTA/Q5-9-11 CLB through the CFSTA/T10_11 CLB.  Therefore, one should route
the Q5 - Q8 signals to the CFSTA/Q5-8 CLB.  Then direct connect the
CFSTA/Q5-8 signal to the CFSTA/Q5-9-11 CLB.  Next, direct connect the
CFSTA/Q5-9 signal with a short net to the CFSTA/T10_11 CLB and then connect
the CFSTA/Q5-11 into the TCB CLB.  Now connect the CFSTA/(T10 and T11)
signals to the Q10_11 CLB. Finally, connect the Q1 - Q4 signals to the
CFSTA/T04Q01-04 CLB and route the CFSTA/Q1-4 signal and the Q0 signals.
For convenience, TCB can be routed to the count CLBs on a long line. It is
recommended that the RoutePin (rp) command in XACT be used to route the Q5
through Q8 signal to CLB CFSTA/Q5-8. Also care should be taken that
additional loads on Q5 through Q8 do not degrade these net delays going
to CFSTA/Q5-8. It is only to get the maximum performance that this hand
routing was done.

Performance:


XDELAY was used to report all clock-to-set-up paths. See the .XRP file.
