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| XILINX APPLICATIONS NOTE XAPP005V V2.00                    BN-3-30-94 |
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README file for the XC3000A register-based FIFO1 and FIFO2:
===========================================================

Note: A more detailed description of this application can be found in
Section8 of theXilinx Data Book.

Files included in XAPP005V.ZIP:
-------------------------------
  
  README          This Readme file
  FIFO1\          This directory contains the 25 MHz 8x8 FIFO
  FIFO2\          This directory contains the 29 MHz 8x8 FIFO
  
FIFO1 
-----

This 8x8 FIFO uses the CE pin of CLBs to enable shifting of data 
inside of the register matrix. Therefore, the FIFO core will use
32 CLBs organized in an 8-columns-by-4-rows CLB matrix. The control
circuitry uses one CLB per word. 

The FIFO will internally run at approx. 25 MHz in an XC3000A-6, 
and at 35 MHz in an XC3100A-3.

Design files included in directory FIFO1:

  SCH\FIFO1.1     Top-level Viewlogic V4.0 schematic
  SCH\FIFO1A.1    Top-level schematic with Input and Output 
		  Synchronizers
  SCH\FIFO8X8.1   8 by 8 Fifo with control logic (Sheet 1)
  SCH\FIFO8X8.2   CLBMAPs for the 8 by 8 Fifo (Sheet 2)
  SCH\ASYIN8.1    Asynchronous input stage, edge triggered
  SCH\ASYSIN8.1   Asynchronous input stage (see below)
  SCH\ASYOUT8.1   Asynchronous output stage, edge triggered
  SCH\ASYSOUT8.1  Asynchronous output stage (see below)
  SYM\*.1         Viewlogic Symbols for FIFO and I/O Stages 
  WIR\*.1         Viewlogic Wire files

  XNF\            Xilinx Netlists 
  FIFO1.LCA       Placed and routed LCA file
  FIFO1.XRP       Xdelay timing report using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Implementation Hints:

The critical path in the control circuitry of the FIFO is detemined by the
delay from POP to the clock enable of the first column of flip-flops. 

The XNFMAP partitioner groups two bits of one word into the same CLB because 
of the naming of the bits (Q0_0 and Q0_1, Q0_2 and Q0_3).  Both registers in 
one CLB can use the same CLB CE pin.

Because the CE pin is used, PPR automatically lines up the registers in 
columns. 

The speed of the FIFO could be further increased by handplacing the 
control CLBs on the bottom of the FIFO such that a minimum of interconnect 
delay is introduced into the critical path. 

The nets in the critical path are:
    FIFO8X8/VALID and POP
    FIFO8X8/SE_6  
    FIFO8X8/SE_4  
    FIFO8X8/SE_2  
    FIFO8X8/RDY.

The FIFO uses CLBMAPs to densely pack the logic of the control circuitry
into CLBs.

The word width of the FIFO core can easily be changed by copying one or
more rows and adding them on to the core. The naming of the new row(s) is 
important if register grouping and regular layout is desired. 

The depth of the FIFO can be changed by adding/deleting of columns. 

There are four additional functional blocks included:

1.ASYIN8 is an asynchronous input stage for an 8-bit wide FIFO.
  It allows a word to be written into the FIFO with an asynchronous input
  clock. RDY signals that the FIFO is ready to receive a new word.
  Note that IOB flip-flops could possibly be used to implement the data 
  holding register if the data comes from off-chip.

2.ASYOUT8 is an asynchronous output stage for an 8-bit wide FIFO.
  It allows a word to be read from the FIFO with an asynchronous output
  clock. OUTRDY signals that the FIFO has a new word available. 
  Note that IOB flip-flops possibly could be used to implement
  the holding register for the data if the data goes off-chip.

3.ASYSIN8 is an asynchronous input stage for an 8-bit wide FIFO.
  It allows data to be written into the FIFO from a system that is not
  synchronized to the FIFO's internal clock. 
  RDY signals that the FIFO is ready to receive a new word.
 
4.ASYSOUT8 is is an asynchronous output stage for an 8-bit wide FIFO.
  It allows a word to be written from the FIFO to a system that is not
  synchronized to the FIFO's internal clock. 
  OUTRDY signals that the FIFO has a new word available. 

The schematic FIFO1A shows how to connect the input/output stages to the 
FIFO core.

Performance:

XDELAY was used to report all clock-to-set-up paths. See the .XRP file.

FIFO2
-----

Compared with FIFO1, this implementation of the logic results in a higher
speed at the same CLB count. The implementation is somewhat more difficult, 
but shows how to take advantage of the LCA architecture as well as advanced 
software tools.
  
This 8x8 FIFO does not use CLB CE pins. Therefore, the FIFO core can use
32 CLBs organized in a 4 columns by 8 rows CLB matrix. The advantage is a 
gain in speed because the critical path of the FIFO now can be implementad 
in adjacent CLBs with no interconnect delay. The control circuitry uses 
one CLB per word. 

Design files included in directory FIFO2:

  SCH\FIFO2.1     Top-level Viewlogic schematic
  SCH\FIFO2A.1    Top-level schematic with Input and Output 
		  Synchronizers
  SCH\FIFO8X8.1   8 by 8 Fifo with control logic  (Sheet 1)
  SCH\FIFO8X8.2   CLBMAPs for the 8 by 8 Fifo     (Sheet 2)
  SCH\SR_CE2.1    2-Bit S/R with non-shared CE in one CLB
  SCH\ASYIN8.1    Asynchronous input stage, edge triggered
  SCH\ASYSIN8.1   Asynchronous input stage (see below)
  SCH\ASYOUT8.1   Asynchronous output stage, edge triggered
  SCH\ASYSOUT8.1  Asynchronous output stage (see below)
  SYM\*.1         Viewlogic Symbols for FIFO and I/O stages 
  WIR\*.1         Viewlogic Wire files

  XNF\            Xilinx Netlists 
  FIFO2.CST       Constraints file to lock CLBs in place.
  FIFO2.LCA       Placed and routed LCA file
  FIFO1.XRP       Xdelay timingreport using XC3000A-6

Software Versions used:

  DS390 Version 4.1.3a Viewlogic and Interface

Implementation Hints:

The critical path in the control circuitry of the FIFO can be 
implemented in adjacent CLBs using zero delay interconnect.
Therefore, the FIFO speed for an 8-word FIFO is approx. 29 MHz in 
an XC3000A-6, and 42 MHz in an XC3100A-3.

The XNFMAP partitioner groups two bits of one word into the same CLB because 
of a CLBMAP in the macro SR_SE2. CLB PINLOCK flags force the APR router to 
access longlines.

The flip-flops in a XC3000 CLB share the CE pin. The register grouping 
does not allow this pin to be used, since in the design each register 
is enabled individually. Grouping two bits of adjacent words will result 
in a "tall and skinny" FIFO with optimally organized control logic. 
The critical path internal interconnect delays are reduced.

PPR does not recognize the structure of the design. Therefore, the
placement and routing may not be regular. Without placement of the CLBs,
the design speed may be as low as in the FIFO1. 
 
To achieve the highest performance, all blocks have to be locked manually
in place and the critical path in the control logic sometimes has to be routed 
by hand.

The nets in the critical path are: 
    FIFO8X8/VALID
    FIFO8X8/SE_6  
    FIFO8X8/SE_4  
    FIFO8X8/SE_2  
    FIFO8X8/RDY.

The FIFO2.CST file shows how to lock the FIFO elements in a pre-defined 
location: 

    place block fifo8x8/q0_1 : aa;
    place block fifo8x8/q1_1 : ba;
    place block fifo8x8/q2_1 : ca;
    place block fifo8x8/q3_1 : da;
	       .
	       .
	       .

To move the FIFO, editing of this file is required. 

The FIFO uses CLBMAPs to densely pack the logic of the control circuitry
into CLBs.

The word width of the FIFO core can easily be changed by copying one or
more rows, and adding them to the core.  

The depth of the FIFO can be changed by adding/deleting of columns. 

There are four additional functional blocks included:

1.ASYIN8 is an asynchronous input stage for an 8-bit wide FIFO.
  It allows a word to be written into the FIFO with an asynchronous input
  clock. RDY signals that the FIFO is ready to receive a new word.
  Note that IOB flip-flops could possibly be used to implement the data 
  holding register if the data comes from off-chip.

2.ASYOUT8 is an asynchronous output stage for an 8-bit wide FIFO.
  It allows a word to be read from the FIFO with an asynchronous output
  clock. OUTRDY signals that the FIFO has a new word available. 
  Note that IOB flip-flops possibly could be used to implement
  the holding register for the data if the data goes off-chip.

3.ASYSIN8 is an asynchronous input stage for an 8-bit wide FIFO.
  It allows data to be written into the FIFO from a system that is not
  synchronized to the FIFO's internal clock. 
  RDY signals that the FIFO is ready to receive a new word.
 
4.ASYSOUT8 is is an asynchronous output stage for an 8-bit wide FIFO.
  It allows a word to be written from the FIFO to a system that is not
  synchronized to the FIFO's internal clock. 
  OUTRDY signals that the FIFO has a new word available. 

The schematic FIFO2A shows how to connect the input/output stages to the 
FIFO core.

Performance:

XDELAY was used to report all clock-to-set-up paths. See the .XRP file.
